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2020-11-06MLBEDSW-3212 Remove CLI opt ifm-ofm-overlapPatrik Gustavsson
Removed the CLI opt ifm-ofm-overlap Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I23faa0d10c3e71972c543e22e8155086fce73556
2020-11-04MLBEDSW-2412 All constraints have been refactoredMichael McGeagh
All existing constraints have now been refactored using the new framework. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Ic9ba0d7040cb9f114b959a949bfdf777f86752c7
2020-11-04MLBEDSW-3275: Added infinity check for Relu scaling valuesJacob Bohlin
Added a supported_operators check for Relu activation functions. If the scaling value overflows to infinity, it will be placed on the CPU. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I66b7bec062599609aadcbb7531caebbc45a7451f Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
2020-11-04MLBEDSW-1974: Set Scratch buffers sizeJacob Bohlin
Set the actual size of the Scratch and Fast Scratch buffer and remove both Scratch buffers from the subgraph inputs. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I9e4213f48289d9136cdd4cd43c668d37c6af8530
2020-11-03MLBEDSW-2868 Separate scale+bias tensorsPatrik Gustavsson
Separate scale+bias tensors by different equivilence_id. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I674341950bc001ac6e4015206995f048a0dfee75
2020-10-30Vela: Fix wrong bandwidthDiqing Zhong
- copy bandwidth compression rate when weight tensor is cloned Signed-off-by: Diqing Zhong <diqing.zhong@arm.com> Change-Id: I41c4c1f7001e8dc12af35695f5f5d02815e28351
2020-10-28MLBEDSW-3212 Enable overlap of elementwise input/outputPatrik Gustavsson
Enable overlap of elementwise input/output Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I6e6f11953319c843c8203bf038f96778df194332
2020-10-26MLBEDSW-3283: Bug fix: StridedSlice Op is placed on CPUDiqing Zhong
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com> Change-Id: I91a3b277cda91dca3bad38908d4ed11a4f5d7d5f
2020-10-22MLBEDSW-3285: AttributeError Tensor has no attributeTim Hall
- Fixed typo in Tensor.is_quantized() Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I36156a6aa5aaff01c4f271a6a8325636173225f3
2020-10-21vela: Refactor operators to use Kernel objectsTim Hall
- Normalise kernel availability by requiring all operators offer a kernel describing how much data they consume from the source, per OFM element, regardless of whether kernels are relevant to the operation. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Idbcff64879fc2eccf292b6208a7d2038eb388017
2020-10-21vela: Improve the scaling is equal checkTim Hall
- Fixed and documented both tensor and quant params scaling checks - Added quant params validity check and tensor quantisation check - Added valid tensor checks to some graph optimisation functions Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I8d6e8f03a603d28886dde511672c8399c85b794c
2020-10-21MLBEDSW-603: Improve cycle estimation in elementwise opsDiqing Zhong
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com> Change-Id: I9f3671041c2b1497519cf42b5f52e3cd01d9c10a (cherry picked from commit e8c989f5236cce12d07a6644329935dbbf0ee8e6)
2020-10-20MLBEDSW-3268: Refactor mark_tensorsLouis Verhaard
- Refactored mark_tensor_purpose - Initial weight compression is now always done in insert_dma - Removed mark_tensor_format Change-Id: Ic719b9bcd1d27e1390d7b9ce8cd21795139ec814 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-19MLBEDSW-3194: Updated elementwise IFM banks countAndreas Nevalainen
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: Ie404a0c13e7c7de0eff649f77e0147a0f3d73acd
2020-10-19MLBEDSW-2412 Refactor constraints for conv opsMichael McGeagh
Using a new system to report constraints, replaced existing functionality for checking conv-like ops. This new system will allow reporting of all constraints regardless of any input network. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: If81177deca2a3b57c9dd9a3a08868cbc9cef0c23
2020-10-16MLBEDSW-3004: UnpackReshaped can't be serialisedDwight Lidman
This commit fixes a bug where a rewritten Unpack operator is placed on the CPU and crashes Vela during serialisation due to the type having changed and there not being a mapping for the modified op type. The solution is to move the fixup_unpack_output function to the graph optimisation pass B, allowing the supported op check to run before it. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ic6bd4c70a478fd61adf377cb487f5b9253130314
2020-10-15MLBEDSW-3219: Suppress CPU info Const/PlaceholderLouis Verhaard
Suppress info print that Const/Placeholder/SubgraphInput are not supported on the NPU. Change-Id: I6f323b64185b01b619b584c1473ae61d010ab3a4 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-14Revert "MLBEDSW-3219: Suppress CPU info for Const/Placeholder"patrik.gustavsson
This reverts commit 04986c0016e59993563490fe67052371fc0e1ad2. Reason for revert: Merged by mistake Change-Id: I150ad9ba7074ad1e80f21180aeba56a454d9f748
2020-10-14MLBEDSW-3219: Suppress CPU info for Const/PlaceholderLouis Verhaard
Suppress info print that Const/Placeholder/SubgraphInput are not supported on the NPU. Change-Id: I689d25481df0cd10487484c9f639e4253df081ee Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-13vela: Improve extra info in constraint checksMichael McGeagh
Keeping the constraint functions consistent with each other Added specific tensor names in the extra info Added operator name to the warning generated This should help easily identify specific problematic nodes in a graph and give a good enough explanation as to why they are placed on the CPU Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Ie5bbdd31e5e75fe37e3d8bb8fee1d260080bce83
2020-10-13MLBEDSW-3219 Added info print for unsupported operatorPatrik Gustavsson
Added info print for unsupported operator Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I1002d1c2249661bff17ef86d9500d1aeb2a1e38e
2020-10-12MLBEDSW-3230 Remove restriction of batching 16 for FCPatrik Gustavsson
Vela supports batching of FC, restriction removed. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ica56738f1b2676628644fc44f2039a24807f5ccb
2020-10-12MLBEDSW-3220: missing "fused_activation_function" caused crashLouis Verhaard
Vela could crash in operator serialization if "fused_activation_function" was not set. Change-Id: I7f2364b0849fd371dee87e26c6d33d44ce8cec26 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-12MLBEDSW-3154 Bug fix for LUT ops with IFM from SplitSliceReadLouis Verhaard
- Incorrect length check in high level command stream generator - Improved tensor names related to LUT based operations Change-Id: Ib8844a35a986e2dbef095df23f143f4633b255f9 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-12MLBEDSW-3061: Update supported_operators.pyDwight Lidman
This commit changes and amends some parts of the restriction functions in order to make sure operators are correctly placed. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I336cf33a874c9078a5bbf81ce129ff917dbc5e9a
2020-10-09MLBEDSW-3218: Added operator indices Quantize/DequantizeLouis Verhaard
Change-Id: Idcf1665f95ddecc2a12ff0e714f645263981d501 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-09MLBEDSW-2985 Avoid reshape if input when there are no valuesPatrik Gustavsson
Added check so that inputs with no values are not reshaped. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Id5e53b093508583c2d70ba7e337869db3de32701
2020-10-08MLBEDSW-3148: Refactor OperationLouis Verhaard
- op.type is now an enum instead of a string - Removed unused operator codes - Refactored some attributes like npu_block_type, fused_activation_function - Refactored operator index calculation - Refactored a number of operator sets Change-Id: I641f65ee375794b7aec42abc0664251ae37d78e8 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-07MLBEDSW-3154 Fix issue for checking axis in concatPatrik Gustavsson
Fix issue for checking axis in concat, now allowing 0. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I85a5fc3dacdfc66dc01b0e05048dd100254fddff
2020-10-06Vela: Fix issue with elementwise block config validationTim Hall
- Presence of accumulators in validation was preventing some elementwise configurations from being chosen. This commit sets accumulator requirement to zero before validating the shared buffer config. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Id79f80afb12f77274ade53f7678c3b2e56aef059
2020-10-05MLBEDSW-2412 Replace generic restrictionsMichael McGeagh
A new mechanism to report generic restrictions/constraints for operators has been implemented. Each check is its own defined function, and has a general reason for the constraint defined as its docstring. This allows us to query all reasons up front and report this without having to run through real data to trigger the checks. This is part of a larger refactoring and the specific restrictions will be replaced by a similar mechanism. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Id3fb2639f91cfac5fc5b8c14f7620de1a85972b2
2020-10-05vela: SupportedOperators promote to class instanceMichael McGeagh
Part of larger refactoring. The sets of operators do not need to be instance attributes and are not expected to be modified at runtime. This in turn allows almost all functions to become class methods. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I7dc24d65cdd6c4bda641b3d6133b3134302a552f
2020-10-02MLBEDSW-3060 Adjust check if weights fit in sramPatrik Gustavsson
When deciding if weights fit sram: A compression of the weights has been added when a weight compression test limit makes it impossible to fit weights in a double buffer in sram. The worst compression ratio from compression, is used to decide if weights can be fit in sram. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I9458769866b3f9fc15659185aae09658ed10fb38
2020-09-30MLBEDSW-3153: Fix overflow in sigmoid LUTLouis Verhaard
Overflow could occur in the calculation of the LUT table for sigmoid, for big negative inputs. Change-Id: I62a33c68de03e9a7a7e4fe2cbd5835c384dc3643 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-30MLBEDSW-3001 Fix Min Max OPs not properly checkedPatrik Gustavsson
Min and max operations was not passed through the checking of elementwize OPs in the supported operator checking. Changed so they are passed through this check as well. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I358a121de33882802415d97d9ed5dbee53233f77
2020-09-30[MLBEDSW-2802] Fix 5D tensor crashFredrik Svedberg
Fixed crash in networks with 5D tensors. Fixed crash for (int32) tensors without quantization. Added validity checks for concatenation. Moved unfusing of activation function from tflite_reader to graph_optimiser. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: Ib9ba8891dc95ef5491e15d0feedef44331a26393
2020-09-30MLBEDSW-3025: Remove SHRAM from reportsLouis Verhaard
SHRAM is removed from performance reports, as the SHRAM numbers only include LUT usage. Change-Id: I5d92bb3be9c8e38dad26ac8ef97c84ecb0aff2fa Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-29MLBEDSW-3032 Fixed issue in removal of reshapesPatrik Gustavsson
Fixed issue in removal of reshapes Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Id6081de8d6b7b6815cc5e56881c20e075214c407
2020-09-29MLBEDSW-2031: LUT support tanh/sigmoidLouis Verhaard
Uses LUT for int8/uint8 based tanh/sigmoid. Change-Id: Ib6ac5a5c958ab9a17e47f620b22c3e22d8d60321 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-28MLBEDSW-2885: Fix overflow from inf numberAndreas Nevalainen
Added check for inf numbers for all scales. Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: I84fcae429be4869d8489f66bef26863c254104cd
2020-09-28MLBEDSW-3035: Updated StridedSlice checksLouis Verhaard
Updated supported operator checks for StridedSlice: - allow negative indices in begin/end values - added more checks on shapes Change-Id: I3ac76bfa6b313f0e2250f0749f152fb0e3aa033c Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-25MLBEDSW-2811: Add rescaling to ReLus with different scalingAndreas Nevalainen
If IFM/OFM is not 4d rescaling ops are added to ReLus with different scaling. Change-Id: I631d44fc8a51fb476b9f62ef90eda26eef3d35f3 Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
2020-09-25MLBEDSW-2337: Intermediate feature maps in fast storageLouis Verhaard
Attempts to use fast storage for feature maps used in between cascaded passes. This is only relevant for system configurations where feature maps are by default not placed in SRAM, but there is SRAM for fast storage. Change-Id: I207b7cf32cfcb5bea3e6b93c2da1161c4af5221d Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-24MLBEDSW-2788 Fix crash on non-constant weight tensorsAndreas Nevalainen
Change-Id: I750ec63a0e37b38feaf4cbdcc883fdbef92bccdf Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
2020-09-23MLBEDSW-3018 Change to check for avoiding NHCWB16Patrik Gustavsson
Fixed issue with checking if axis corresponds to C-dim Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I72d9fd2c9fca642b5ab326324a63111b01c5de98
2020-09-23MLBEDSW-3070: Fix addressing of weightsLouis Verhaard
Assign different equivalence ids to weights with same values but different compression, to ensure correct addressing. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I13aabad71520e4f4a78fb2d6a81740bdd4d1256c
2020-09-22MLBEDSW-2813: Handle non-const weights and check shapesAndreas Nevalainen
- Added check for non-constant weights in supported operators - Added check ifm & ifm2 shapes - Handle None tensors for CPU operators - Handle missing attributes for Cast operator Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: I2f16d3d44d0c6da5237550b39273cdb9cc3c7607
2020-09-21Fix int8/uint8 softmax mul shapeFredrik Svedberg
Fixed incorrect ofm shape for some of the intermediate mul operations in softmax int8/uint8. Change-Id: I82351c1eb6a66b93280752f4cc00e2d0744d33b2 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-09-21MLBEDSW-1693 Convert batched FC to ConvPatrik Gustavsson
Added support to convert batched FC to conv. This enables choosing a suitable block-size. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Idc49e4fb6d29c554f10a38ece7996a7b7795ffad
2020-09-21MLBEDSW-2816: Fix assert in schedulerDiqing Zhong
- Use non local memory as the base sram usage for a subgraph - Make avoid_for_spilling more generic for all mem configs Change-Id: I99cd30fe6a8ba075d5a70dc2138aa0635afaadb3 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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