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- RSQRT is only defined for positive numbers and
therefore the zeropoint and actual input value
will have an impact
- Clamp the range to avoid crashing. As long as the actual
input is within valid range everything works. If the input
is not valid the reference will crash and not generating
any output
Change-Id: I1082b508d9cd85ad4b017e7b786cfff730585172
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- now only converts array directly if ndim==0
Signed-off-by: William Isaksson <william.isaksson@arm.com>
Change-Id: Id23e419bc7dd717f9694013180d4609819fd2f56
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- npu_performance now uses write/read shapes instead of using ifm/ofms
for memory cycle estimations.
- also fixes a would be bug in the tflite_graph_optimiser, where one
read shape is not Shape4D.
Change-Id: I2067069a713d2cf9e65a5cc227e803de79940fff
Signed-off-by: William Isaksson <william.isaksson@arm.com>
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PAD input tensor shape plus paddings must equal output tensor shape.
Change-Id: Icc5dea9bf6a8f6e1c8402f4d9af4d9796e8ef1aa
Signed-off-by: Johan Gunnarsson <johan.gunnarsson@arm.com>
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- Documented High-Level and register-Level command stream options
- Changed High-Level command stream display to show the name of the
command
- Fixed an issue with some operators not being displayed by the
CLI option --verbose-operators
- Changed an unneeded print in pass packing to a more useful assertion
Change-Id: I9d53f19f4e32d0478209bc964724c27c935f66d6
Signed-off-by: Tim Hall <tim.hall@arm.com>
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We now don't rewrite tensors if the tensor is already an output tensor of the current subgraph
Signed-off-by: William Isaksson <william.isaksson@arm.com>
Change-Id: I9cb36d830616a69d35180326437ff53bcaa62d71
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Adds Vela version to description and metadata
Change-Id: I75fccd1a05a396612a249b8ec1662d8cae940ee6
Signed-off-by: William Isaksson <william.isaksson@arm.com>
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- Added support for multiple npu subgraphs to have the same cpu output tensor
Change-Id: I2e787306dd64af9b03cdf2bacb4c9ff7119f6c49
Signed-off-by: William Isaksson <william.isaksson@arm.com>
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Performance estimation now uses the parent_tensor mem_area instead of
the scheduler_op mem_area, because the mem_area is only set on the
parent_tensor by the scheduler.
Signed-off-by: wilisa01 <william.isaksson@arm.com>
Change-Id: I11f73686bfbd6958a8920c5e264a5f95cc3f23d1
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- checks that cmd1 payloads are legal in
register_command_stream_generator,
- adds unit tests
Change-Id: I2bc23147f60fe090c71703f08d9cbaa279fac86e
Signed-off-by: William Isaksson <william.isaksson@arm.com>
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- Updated FlatBuffers files using TensorFlow 2.12.0 schema
- Added restriction for UnidirectionalSequenceLSTM to have 2D recurrent
weights to handle that diagonal_recurrent_tensors attr is not
currently supported.
Change-Id: I104fd1f52485b9b83d644772dbcdeea2d17585f0
Signed-off-by: William Isaksson <william.isaksson@arm.com>
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- Added graph optimiser function to convert convolution groups into
a split followed by separate convolutions and then a concat
- Added semantic check for convolution groups
- Added unit tests for convolution groups semantic checks
- Fixed a minor typing issue with test_constraint_stride_range
Change-Id: I78ade408aa23469a79c9f517c4751da8619b77a9
Signed-off-by: Tim Hall <tim.hall@arm.com>
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If any of H,W axes have shape 1, the IFM can be reshaped to support
reduction over the depth axis.
Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com>
Change-Id: I432ff1c399b7cee4ca5f0a8f4461e9c0a936d804
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- Add support for batch and depth channels when shape is 1
- Refactor reshaping in convert_mean_to_depthwise_conv
Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com>
Change-Id: If663395934ab58c76ba92b6ebaaf484a389ae699
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* Fix bug in register_command_stream_generator where certain
high-level command streams resulted in missing DMA_WAIT commands
* Add unit-tests for DMA_WAIT and KERNEL_WAIT commands
Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com>
Change-Id: Iabb3ea3e95fa1ef933c50356d047b6b3f5aeafe3
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- In order to reduce memory usage, the live range mechanism have logic
to check if the ifm tensor can be reused for the ofm tensor for certain
operators
- In this failing test case, the input to the reshape/memcpy operator
has more than one consumer and this results in a faulty memory overwrite
since there are missing logic that should check the ifm consumers for
the memcpy operator
- The fix is to add the missing logic that ifm can only have one consumer
Change-Id: I2184c0f905b554f648c9732734098509e23b537c
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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Changes query initialization shapes to Shape4D(0,0,0,0) = [0,0,0,0]
instead of Shape4D(0) = [0,1,1,1]. The [0,1,1,1] tensors would affect
performance estimates and are not real.
Change-Id: Ic83b6f6a70c0c904b500f62756e1e125c99856c6
Signed-off-by: William Isaksson <william.isaksson@arm.com>
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- The problem is that the axis value can be either a scalar or an
array containing a single element
- The solution is to check the length of the shape because the size
attribute returns the same value for both cases
- This did not show up before because pytest warnings were not being
treated as errors
- Removed pre-commit pytest option that caused tests to be searched for
from the root directory
- Updated pyproject.toml pytest options to explicitly specify the test
directories, and to treat warnings as errors
Change-Id: I037054768e5c34f253b6062eadba1c3419ff65e4
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* Improve check_cmd functions to return position of the checked commands.
* Update existing unit-tests to validate ordering of commands.
Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com>
Change-Id: I492487d768e1e80f6ea366e29f2f99441e4f9797
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Add function description and type annotations to the optimization
functions missing them.
Fix type annotation issue when re-assigning variable
value to a different type.
Change-Id: I1ee442ff7a29cc07708fdd013430131eff599dd5
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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* Convert Means with large IFMs to several DeptwiseConv2DBias and Add
operations.
* Update tflite supported operator check with new height and width
constraints.
* Update unit-tests to verify supported operator changes.
* Fix output-diff for 2D IFMs (MLBEDSW-7772)
Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com>
Change-Id: Ifae6fb1cdac475ae7dac5116c5f13631ff82108a
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- A crash occurred due to NoneType subscriptable error when
rewriting a Slice op. The reason was that the Size tensor did
not contain any data.
- Added constraint pushing the Slice operator to the CPU if
begin or size tensor are empty.
- Added test to supported operators
- Updated SUPPORTED_OPS.md
Change-Id: Ide204cae24e5871f0e6ae1fdc98ac68d0ce4d3ae
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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* Convert AvgPool with stride_width > 3 and Valid padding to Conv2D to
optimize it to run on NPU.
Change-Id: I06ab412357f0b09b1498f9019a9d1963a324ad34
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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* Fix bug that caused filter padding to not be added proportionally
compared to the hardware padding added to IFM.
* Update needed_total_padding function that calculates hardware padding
to also account for the cases in which IFM width is not divisible by
the stride width.
* Update supported ops constraint on strides for conv2d to mark ops with
stride width > 3 and IFM width that is not divisible by the
optimization resize factor as not supported.
* Update unit tests that verify correct functionality when checking
whether ops are supported or not.
Change-Id: I62f14cca890b779ca787a9603fa37c873ad522f8
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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Change-Id: I4f466a7bac77d8bb6fa7243ea2e7c9f3be6d0585
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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Update import of Sized from collections to collections.abc to work with
Python 3.10
Change-Id: Iae281db9402331972ad13660d04523608b23614d
Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
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- Added RSQRT int8 support, implemented as LUT.
- Added test to supported operators
- Updated SUPPORTED_OPS.md
Change-Id: I34904772e044be8d22a6dfe426edf85358a205b7
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- When optimizing for Size the scheduler does not try to add weight
buffering to the schedule since this would add extra SRAM usage to
the peak usage. However, for all other ops that uses less SRAM than
the peak there is memory available that could be used for weight
buffering and hence improve the performance.
- Removed limitation to only run optimize schedule when optimizing
for Performance. Regardless of optimizing for Performance or Size the
scheduler flow is the same except that the limit for max SRAM usage is
different.
Change-Id: I6880b35655e37b4916a9c15150f0b8e5126a1cd8
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- Cascading was recently enabled for Resize ops. A Resize op is
transformed into several ops. In this case the last op is a
DepthwiseConv2DBias using NEAREST resampling mode. This resampling/
upscaling is not taken into account when calculating the ifm box
size, causing the coordinates to get out of bounds.
- When generating the high level command stream there is a check to
see if an op is a resize op. If this is the case an upscaling factor
is calculated. The fix is to change this check to instead see if the
operator is using NEAREST resampling mode. If that is true, the
scaling factor should be used.
Change-Id: I5308a383cc3310c53004ccfe2d6fabf256478a26
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- Added fix when building the minimum schedule forcing the stripe
to be even for is_nearest ops. This is required in order to be
able to allow cascading for resize ops.
- Remove limitation in cascade builder that prevents resize ops
to be cascaded.
Change-Id: I05150102b91531ecba786936494f1817a4472f42
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- Added release information
- Minor changes to SUPPORTED_OPS.md including version info
Change-Id: I91fae4c40c6c1f25b874268b18d077a9babd4875
Signed-off-by: Tim Hall <tim.hall@arm.com>
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half_pixel_center=True
Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com>
Change-Id: I0e9db22c97a9e2fbfee618262ffc43532cfcee2c
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Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com>
Change-Id: I35fd042d572f62122ac681c231798c9f2163fc00
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- Fixed an issue with the fusing of PAD and AVERAGE_POOL_2D whereby
the rounding away from zero didn't work because it requires the zero
point to be at zero but the input padding required it to be set to the
desired zero point. This affected both int8 and int16. The solution
was to remove it by using the bias prior to the scaling
- Refactored the rounding away from zero mode
Change-Id: I8f2df69df06d2a9722315c346646e5a901cb2c3b
Signed-off-by: Tim Hall <tim.hall@arm.com>
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Fixed serializing of attribute container and shared_name that
accidently got lost when fixing the crash for a faulty LSTM model.
Change-Id: Ibd11da65735112bed4b1c8bcc4ef048bc093ebc4
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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* Fix import order in test_build.py
* Fix setup_tools_scm dependency version. Previously the version was
restricted to < 6, creating a version restriction on Setuptools
library too.
Because an older version of Setuptools was used, running
test_build.py::test_build_correct_readme_links would generate a
UNKNOWN.egg-info directory in the src directory instead of a
ethos_u_vela.egg-info directory.
Change-Id: I113ca25b23b39d43fa288e6eda16377f4f5b4143
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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Add --verbose-progress CLI option used to enable printing progress
information in the compiler driver and scheduler.
Change-Id: I99ac8c6a654e60391d5c11e28b89250405daa53a
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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Remove unused parameter rescale for faf
Change-Id: Id388d307f3eb0d27bce813ab58e3c9a5f4ba89ae
Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
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* Implement a general optimization solution for strided CONV2D that
supports a stride_w with no upper bound.
* Implement filter zero padding to allow for optimization in those cases
in which the filter width is not divisible by the stride width.
E.g.: Filter width = 8, stride width = 3 ->
Filter width = 8 + 1 (0 padding) = 9, stride width = 3
* Implement partial optimization to reduce the stride to hw supported
strides (i.e. 2 and 3) when optimizing to reach a stride = 1 is not
possible due to the IFM width not being divisible by the stride width.
* Implement optimization for when SAME padding is used. If the pre-opt
and post-opt padding do not match, add zero padding to the filter so
that the post-opt IFM padding matches.
Change-Id: Ia66b0d107281fa9993f6bf4d0c26627ee743253b
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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This reverts commit 72c6a2414205e033279f80b622cdf479c05a4f5b.
Reason for revert: Fix performance regression caused by breaking cascades in certain models
Change-Id: I5aba6e3c59ab27c5129f4a3f0c320ed18df78943
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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- The reference calculates the rounding different between
int8 and int16 for Conv2d. However, internally a Conv2d can be
changed to a FullyConnect but then the rounding must still be
calculated following the Conv2d reference.
- The fix is to check the original type if NATURAL rounding
should be used or not. int16 Conv2d uses NATURAL rounding
in reference.
Change-Id: I80d48b54372ef7b978ee2e9384a01934dd454e24
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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Updated the Q0_15_SCALE constant to match the updated value
in the reference.
Change-Id: Id680748c532d41fea9760ec76c0b65c0c3e73a13
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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Treat Dynamic Weights as FeatureMap to avoid issues during scheduling
caused by having non constant OPs that produce tensors used as weights.
Change-Id: I2b9ee7fb62a150c5052c6c3b1a6d34f22e9426a9
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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- The reference calculates the scale slightly different between
Conv2d and FullyConnect. Recently a fix was submitted to address
this issue. However, internally a Conv2d can be changed to a
FullyConnect but then the scale must still be calculated
following the Conv2d reference.
- The fix is to check the original type if FullyConnect scale
should be used or not.
Change-Id: I5a9fb49126f0df63712b73fb5520fdc604cee378
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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We now read operator code version, store it in operator and write it out
to optimized file.
Signed-off-by: wilisa01 <william.isaksson@arm.com>
Change-Id: Idba672531d2e2a0203a85d3ffca9cf65ace85b47
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Change-Id: I50b85953bff13bd6ec0648dec5d86b8ac749137a
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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* Add test to verify that the metadata produced in the PKG-INFO file of
the sdist contains the correctly formatted links extracted from
README.md
Change-Id: I300094470fd115b1143aa8c663837e8a77428f24
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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removed redundant row
Change-Id: I8b90df3b45ed863c93572b33f695b06094103015
Signed-off-by: wilisa01 <william.isaksson@arm.com>
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fixed by using sched op instead of last pass op
Change-Id: I2e03d39462ca07372d85c71e78189bd8c58a1b9c
Signed-off-by: wilisa01 <william.isaksson@arm.com>
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- The assert triggers when a constant tensor is being assigned
to buffer 0 and that is a violation.
- The test case that triggered this problem revealed an error in
the reader code. If the input tensor has constant data it should
be using a Const op. Before this fix it was assigned a
Placeholder op and the tensor ended up in the scratch area
instead of the permanent area.
Change-Id: I4f92fb5ec1f0dc594defbaca0335eabe68fd5137
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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