Age | Commit message (Collapse) | Author |
|
*lint
*added unit tests
*added typecheck
*added docstring for the api
Change-Id: Ibd4bc40d4381ac40ad2ea3d500b26c4ec565ab07
Signed-off-by: Manupa Karunaratne <manupa.karunaratne@arm.com>
|
|
This commit adds a quantization restriction check
for supported operators, so that operators with
different quantization between its IFM (1/2) and
OFM tensors that do not support it, are correctly
placed on the CPU.
The quantization between two tensors is compared
using a new equality function implemented for
the QuantizationParameters class.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I70ff36b4ab4955f328d6e6e699f00dbc43c0404a
|
|
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: Ia9c70d62c6abc827cbdf73a8bb37afd595796741
|
|
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I39cff126dda89d71426ab731427ca1d64d02590d
|
|
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: Iaf4d7ab9c32b0d783072c5f131a61bfebe77cc16
|
|
Automatically generated, no functional changes.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: Ia6a791f7dbadc352bc8a7b528afa070e8540b4d0
|
|
Avoid encoding empty weights stream.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I120ede14f19705e169c5f03ed344036a58b5f84f
|
|
Fix for alignment of tensor for bias and scale
Change-Id: I303a225a536f169909cec9ba4d5cee088110bb94
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
|
|
- Fixed bug with the size of the scale and bias tensor
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I4d267d4c918a5c834ebdff82de4f021717e95203
|
|
Added support for one more memory configuration-
Change-Id: Iac19992386e3e9b80bd519acb1b0a399c47d736f
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
|
|
This will give a worst case estimate of the Double Buffer size in the
Scheduler and it will no longer be able to choose strategies that end
up with a buffer that doesn't fit in SRAM.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I763731f63c7672679f3b8cd6db65dad03b946ae5
|
|
- Parallelism mode register was being written for non Yoda targets.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I31b50031dab4d615733c4c3790dec8934117f275
|
|
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I53d9d56acee57cff208dccb4822c1f1a461c416d
|
|
Restrict settings of permanent storage.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Iaa81ee05e8e567b2737825be634baa9085192f0e
|
|
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: Ief50c934b9e9b0bd3024d3ed0bbaa7b655971952
|
|
- If blockdepth or core count resulted in empty or non-existent substreams, the
command generator generated an error. This commit changes the command stream
generator to only program cores that have streams and are enabled for the
configuration.
Change-Id: I4e724b19de14d3a12e886ec6b17d0038593dfb59
Signed-off-by: Tim Hall <tim.hall@arm.com>
|
|
- Multicore weight and scale stream interleaving for
multicore hardware architecture.
Change-Id: Ic82850463391c629d90d08c26cf0c48dd438286d
Signed-off-by: Tim Hall <tim.hall@arm.com>
|
|
Additional supported memory configurations:
-Permanent_storage = DRAM
-Tensor arena either in DRAM or SRAM
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I20beb7151e306bfdba540e7c0b2a7b478b4d94e1
|
|
Added more accelerator configs.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I77a5ece0b9ed1eddb9b8aa9bb7656a022df95fd6
|
|
- Includes npu_active event
Signed-off-by: Douglas Troha <douglas.troha@arm.com>
Change-Id: I9a2e342a11b9cc2a51f42141edb6f1a4fb4725e7
|
|
- A blanket exception was preventing block config overrides from being used,
from either code or command line.
Change-Id: I1a7aa7771e077bcdb66886a6b637d099ae43d732
Signed-off-by: Tim Hall <tim.hall@arm.com>
|
|
- Fixed custom operator pass through
- Added error printing functions for operators and tensor
- Minor cleanup of custom exception handling
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Idf295df1e4c544381dc480244d880c32fb285e38
|
|
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I6e8a97486aa2e1a21101f7cc32cd3024a376162a
|
|
- No functional change
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I5ab1198b9d092cd041fa9b85b2dee9900d299bfc
|
|
- Added support for HardSwish (placed on CPU)
- Improved error reporting for unknown operator codes in input file
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I1d1c7b9d786288d7098450cdad2b67fc0759378b
|
|
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I92b18262608415e84266d2903e17fc5112793a38
|
|
Fixed a coordinate issue which caused the compiler to crash when
cascading upscaling operators such as ResizeBilinear.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I982863573b0e5829e6d0c255dbbc308cb332a37a
|
|
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I78f475f9837a7c11f01b2693b17efe1a7c6481cc
|
|
Make it configurable for using NHCWB16 between
cascaded passes.
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I259cdaa424d11ea38f17e671490ad1e630bbae44
|
|
This commit places LeakyReLU operators with
a negative alpha value on the CPU and avoids
a crash during command stream generation.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Iac68c5a9fdbf26facb709660965615b2b5b551f9
|
|
Bug fix in the generation of the NPU_SET_IFM2_SCALAR parameter.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: Ie261a90dcfa61ed269d27a100eb48c58af8a325d
|
|
Tensors that are the result of an operation were incorrectly marked
as scalars.
Also fixes a bug for IFM2 of shape [*,*,*,1] in elementwise operations.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I82a0e643b12e93c7158e4aca3185415c59033a73
|
|
- Removed --inter-pass-cycle-delay
- Removed --dram-bandwidth
- Removed --batch-size
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ib613f47a9e911c652e522b5aa9ec58ae5391b0fd
|
|
Kernel height was not correctly calculated for pooling
operations in rolling_buffer_dims_from_passes.
Change-Id: I48763b4b3276538c111e6699f66636327e569705
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
- Add support for marking the tensor purpose of CPU only ops such as LESS which mark their input based upon their output
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ia7898089f0b18ccd4f183e2ef961a67f4d169e4c
|
|
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: Ib8d66f8b3c0467966165c1b53aeb7da7c8764c89
|
|
- Fix various problems when no operators run on Ethos-U55
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I44a1a914fabb7ca26c921a02753da8abeecd9c7b
|
|
Change-Id: Ie6d8d6de9f3447f19ba06aafa9fa480fc96a973b
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
|
|
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: Ia7127148d00280bf9c3759dd6dcbe500a4cfcc78
|
|
- Dilation added to SET_KERNEL_STRIDE instruction
- Kernel height/width adjusted for dilation
- Updated padding calculation
- Updated weight compression
Change-Id: I0c8190223e223b039a305aba0f37896ae1de2b80
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
If same weight tensor was used with different block configs,
errors would occur.
Fixed by always cloning weight tensors, using a global weight
compression cache and modifying the linear allocator to
detect multiple usage of same weight compression.
Change-Id: I91ca59176e1c59c66e0ac7a4227f2b5f0b47053f
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
This commit fixes a bug where there would be an off-by-one error
in some cases for ResizeBilinear.
It is resolved by treating it the same way as an AvgPool in
regards to setting the zero point.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I2835d5dcf360f65e19265c339e5ffd02de16c823
|
|
This commit fixes the failing assert by removing it
and instead placing unsupported ResizeBilinear
operators on the CPU.
It introduces a new graph optimisation function
which adds the necessary attributes as well as
new operator restrictions for ResizeBilinear.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I2feffd0b5a2169ebffbe4f165e450b3f2d140380
|
|
This commit ensures the IFM block size calculation
in architecture_features.py matches the specification
by correctly setting the ifm upscaling factor based on
the upscaling mode.
This requires adding an attribute to the Tensor object
which stores the upscaling mode for that specific
tensor and making sure that information is correctly
carried over to shared_buffer_allocation.py.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I4ab56086f4c694d3bf759bbad30cdb969b4a26db
|
|
Updated supported operator checks according to latest requirements.
Change-Id: I79708d8039e464e39818d3c09e61f3f533e96f3d
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
|
|
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I7b18af503ac6482cf8dc3e9f3e2e93e6cba6426f
|
|
Added custom exceptions to handle different types of input errors.
Also performed minor formatting changes using flake8/black.
Change-Id: Ie5b05361507d5e569aff045757aec0a4a755ae98
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
Write the constant scalars into flash. In case it's Dram
or OffChipFlash, DMA the scalars from flash to sram.
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I42300a05dfe968d623b8aec8549644549e0f54b5
|
|
Fixed scaling for int16 tanh/sigmoid to match the reference.
Change-Id: I3110298b7e8638a82cc05bedc03de389dec27898
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
|
|
Updated the algorithm for SHRAM buffer size calculation with
block depth alignment.
Change-Id: Ie8b10725bb9f52ba4a353b5a2170653833e6e5c0
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|