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2024-02-06MLBEDSW-8620: Fix MirrorPad supported ops checkRickard Bolin
Change-Id: I1458009f4b92c1a599efa3a63d6768148e55606d Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
2024-01-30MLBEDSW-8491: Add support for Mirror padRickard Bolin
Change-Id: I3c13118e14195a5fb8e522a38b205b75fb07b74b Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
2024-01-18CONV ops int16 tests failed after TensorFlow updateWilliam Isaksson
Adds support for setting the accumulator type using the quantized_bias_type attribute Change-Id: Ibde1149143b510a1c650a5a037d3ab92d878d7cd Signed-off-by: William Isaksson <william.isaksson@arm.com>
2023-12-20MLBEDSW-8157: Update to TensorFlow 2.15William Isaksson
Updates to TensorFlow 2.15. No StableHLO operators were added to Vela since these are subject to change and have almost no runtime support. - FlatBuffers version was unchanged. Change-Id: I9a506a2dcc2e0bc2498742e857bbb6d69b19ac1b Signed-off-by: William Isaksson <william.isaksson@arm.com> Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
2023-11-15MLBEDSW-8326: MLCE: Update constraint message for AVERAGE_POOL_2DJohan Alfven
- Added missing constraint message for stride height by adding the constraint_stride_width_no_upper_limit to AVERAGE_POOL_2D Change-Id: Ib716fb19e44cb8735b52270b557998d4cbf5cb1c Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-11-09MLBEDSW-8290: MLCE: Add TRANSPOSE support3.10.0.rc1Johan Alfven
- Added graph optimiser function to convert TRANSPOSE op into an AvgPool op with swapped stride for height and width - Added TRANSPOSE supported op check - Added unit tests for TRANSPOSE supported op check - Updated SUPPORTED_OPS.md - Fixed problem in pass packing when optimizing the pass list. Old problem, but now seen when moving TRANSPOSE from cpu. Change-Id: I0a0ef420b0fb8241090c2e2434622881105cde15 Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-10-31MLBEDSW-8201: [MLCE] Extended stride support for CONV_2DJohan Alfven
- Added support for stride_h > 3 when ofm height is 1 - Added support for stride_w > 3 when ofm width is 1 - Updated constraints - Updated tests - Updated SUPPORTED_OPS.md Change-Id: I8f89909b05a0f052df5f03702966cee50da61cfc Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-10-11MLBEDSW-8111: Update to TensorFlow 2.14Rickard Bolin
- Update to TensorFlow 2.14 and minimum required Python version to 3.9. - Update version pins on NumPy and FlatBuffers. - Add constraint to Offset attribute of StridedSlice operator Change-Id: I8c7122def963202e5f47e92b62be607935ed05cf Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
2023-09-18MLBEDSW-8042: MLCE: Add SQUARED_DIFFERENCE supportJohan Alfven
- Added SQUARED_DIFFERENCE support - Updated SUPPORTED_OPS.md Change-Id: Id83d9d92129e645390c7979759dfdeff7a14c2ee Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-09-12MLBEDSW-7997: [MLCE] Extended stride support for TRANSPOSE CONVJohan Alfven
- Support for stride WxH 1x1 - Support for stride WxH 2x1 when IFM and KERNEL is 1D shape with height 1 - Added test to supported operators - Updated SUPPORTED_OPS.md Change-Id: Ic1abead8399a5e14a78d962f8aded0d3b3dbfcc4 Signed-off-by: Johan Alfven <johan.alfven@arm.com>X
2023-07-24MLBEDSW-7165: Update to TensorFlow 2.12William Isaksson
- Updated FlatBuffers files using TensorFlow 2.12.0 schema - Added restriction for UnidirectionalSequenceLSTM to have 2D recurrent weights to handle that diagonal_recurrent_tensors attr is not currently supported. Change-Id: I104fd1f52485b9b83d644772dbcdeea2d17585f0 Signed-off-by: William Isaksson <william.isaksson@arm.com>
2023-07-11MLBEDSW-7653: Extend Mean support for depth axisAlexander Hansson
If any of H,W axes have shape 1, the IFM can be reshaped to support reduction over the depth axis. Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com> Change-Id: I432ff1c399b7cee4ca5f0a8f4461e9c0a936d804
2023-07-11MLBEDSW-7652: Add mean support for batch and channel when shape is 1Alexander Hansson
- Add support for batch and depth channels when shape is 1 - Refactor reshaping in convert_mean_to_depthwise_conv Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com> Change-Id: If663395934ab58c76ba92b6ebaaf484a389ae699
2023-06-19MLBEDSW-7654: Extend support for Mean where HxW > 4096Alexander Hansson
* Convert Means with large IFMs to several DeptwiseConv2DBias and Add operations. * Update tflite supported operator check with new height and width constraints. * Update unit-tests to verify supported operator changes. * Fix output-diff for 2D IFMs (MLBEDSW-7772) Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com> Change-Id: Ifae6fb1cdac475ae7dac5116c5f13631ff82108a
2023-06-16MLBEDSW-7709: MLCE: Crash when rewriting split opJohan Alfven
- A crash occurred due to NoneType subscriptable error when rewriting a Slice op. The reason was that the Size tensor did not contain any data. - Added constraint pushing the Slice operator to the CPU if begin or size tensor are empty. - Added test to supported operators - Updated SUPPORTED_OPS.md Change-Id: Ide204cae24e5871f0e6ae1fdc98ac68d0ce4d3ae Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-06-16MLBEDSW-7315: Add support for AvgPool with stride_width > 3Raul Farkas
* Convert AvgPool with stride_width > 3 and Valid padding to Conv2D to optimize it to run on NPU. Change-Id: I06ab412357f0b09b1498f9019a9d1963a324ad34 Signed-off-by: Raul Farkas <raul.farkas@arm.com>
2023-06-16MLBEDSW-7648: Fix bug with filter padding in conv2dRaul Farkas
* Fix bug that caused filter padding to not be added proportionally compared to the hardware padding added to IFM. * Update needed_total_padding function that calculates hardware padding to also account for the cases in which IFM width is not divisible by the stride width. * Update supported ops constraint on strides for conv2d to mark ops with stride width > 3 and IFM width that is not divisible by the optimization resize factor as not supported. * Update unit tests that verify correct functionality when checking whether ops are supported or not. Change-Id: I62f14cca890b779ca787a9603fa37c873ad522f8 Signed-off-by: Raul Farkas <raul.farkas@arm.com>
2023-06-14MLBEDSW-7748: Add RSQRT supportJohan Alfven
- Added RSQRT int8 support, implemented as LUT. - Added test to supported operators - Updated SUPPORTED_OPS.md Change-Id: I34904772e044be8d22a6dfe426edf85358a205b7 Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-05-17MLBEDSW-7494: Update release notes3.8.0.rc2Tim Hall
- Added release information - Minor changes to SUPPORTED_OPS.md including version info Change-Id: I91fae4c40c6c1f25b874268b18d077a9babd4875 Signed-off-by: Tim Hall <tim.hall@arm.com>
2023-05-17MLBEDSW-7230: Increase support for 1x1 ResizeBilinear with ↵Alexander Hansson
half_pixel_center=True Signed-off-by: Alexander Hansson <Alexander.Hansson@arm.com> Change-Id: I0e9db22c97a9e2fbfee618262ffc43532cfcee2c
2023-05-10MLBEDSW-7283: Add opt cases for strided CONV2DRaul Farkas
* Implement a general optimization solution for strided CONV2D that supports a stride_w with no upper bound. * Implement filter zero padding to allow for optimization in those cases in which the filter width is not divisible by the stride width. E.g.: Filter width = 8, stride width = 3 -> Filter width = 8 + 1 (0 padding) = 9, stride width = 3 * Implement partial optimization to reduce the stride to hw supported strides (i.e. 2 and 3) when optimizing to reach a stride = 1 is not possible due to the IFM width not being divisible by the stride width. * Implement optimization for when SAME padding is used. If the pre-opt and post-opt padding do not match, add zero padding to the filter so that the post-opt IFM padding matches. Change-Id: Ia66b0d107281fa9993f6bf4d0c26627ee743253b Signed-off-by: Raul Farkas <raul.farkas@arm.com>
2023-04-21MLBEDSW-7408: MLCE: Crash when serialising model LSTMTim Hall
- Added checking and reporting of missing operator attributes when reading and writing TFLite file - Added a TFLite semantic check to ensure that all required attribute fields of builtin operators are read - Added some sanity checks for RESHAPE operators that run on the Ethos-U - Stopped CPU operators from having their attributes modified Change-Id: I05700681acdb09554f5945819717c08a9457295c Signed-off-by: Tim Hall <tim.hall@arm.com>
2023-04-19MLBEDSW-7487: Updated implementation for the Mean opJohan Alfven
- Latest reference has changed implementation for the Mean op and now only contain one variant. - Updated Vela implementation to match reference. The full sum is first calculated and then divided by the numbers of elements. - Removed the avg pool variant and test case. - Updated SUPPORTED_OPS.md Change-Id: I4275e36e3697fa837f119f2cefd7c0ff94231605 Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-04-17MLBEDSW-7196 Add LSTM supportFredrik Svedberg
Added int8 and int16 UNIDIRECTIONAL_SEQUENCE_LSTM support. The implementation does not include support for: * CIFG * Peephole * Projection * Normalisation This change also: * Removed unused Op.BlockLSTM operation type. * Removed the only one consumer limitation on putting the SplitSliceRead on the tensor consumer(s), if all consumers fullfills the requirements * Added Op.VariableTensorWrite as a Operation.memory_function to make sure writes to variable tensors: * Always use linear mode * Are not moved to fast scratch * Are not fused with other elementwise operation tensor ranges Change-Id: Ief831738924ac3d1f2ba6d41f10bd6dc969911f3 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2023-04-12MLBEDSW-7437: Add 64-bit output support for ArgMaxJohan Alfven
- Added 64-bit support for ArgMax - Updated constraints for ArgMax and regenerated SUPPORTED_OPS.md Change-Id: I4ef7d2e6fccab0088b87757f6afe40a006c77bbd Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-03-31MLBEDSW-7439: Add support for input dims < 4 for ArgMaxJohan Alfven
- Updated ARG_MAX to support IFM rank less than 4 - Regenerated SUPPORTED_OPS.md Change-Id: Icd8e72733279413cbea49021325e1ab06fdc6011 Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-03-22MLBEDSW-6435: Implement support for ArgMax along depth dimensionRickard Bolin
- Add support for ArgMax along depth dimension with a depth limit of 127. - Only supports 8-bit input and 32-bit output Signed-off-by: Rickard Bolin <rickard.bolin@arm.com> Change-Id: I5f6f0503135bebabbb1ca637f9729587b7c60740
2023-02-09MLBEDSW-7331: Reinstate max stride height constraint of 3 for Conv2DRaul Farkas
Reinstate constraint for stride height to (1,3) instead of (1,4) for Conv2D and update unit tests. Change-Id: I17389ee040eeff0cea08279cab1c038e951569ea Signed-off-by: Raul Farkas <raul.farkas@arm.com>
2023-02-07MLBEDSW-7237: CONV_2D stride 4 optimisationRaul Farkas
* Extend stride range from (1,3) to (1,4) * Add stride 4 support when optimising CONV_2D * Add some tests for various strides Change-Id: Iddaeb42c4a6e02695ecdd3740bc8b9dd59a7eb3c Signed-off-by: Raul Farkas <raul.farkas@arm.com>
2022-12-09MLBEDSW-7072: Added bias shape constraintJohan Alfvén
- Only 1D bias shape is supported - Modified test to reflect the constraint - Update SUPPORTED_OPS.md Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I00ae4b229d5f89512cb94f87f276af61cc66a6fd
2022-11-16MLBEDSW-6620: Update copyright notice and yearsRickard Bolin
- Update copyright notices to use SPDX format and add OSS mail as contact. - Update years on files where it had been missed. Signed-off-by: Rickard Bolin <rickard.bolin@arm.com> Change-Id: I7e9715ea4e17b76252728c708e46df12ad67ab1f
2022-11-15MLBEDSW-6905: Add dilation greater than 2 supportTim Hall
- Added graph optimisation pass to support dilations greater than 2 in either dimension - Removed supported operators restrictions - Removed erroneous dilation on TRANSPOSE_CONV - Updated unit tests and documentation Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ide302374b0d5eff25c20501383a63f6aa7625c52
2022-11-03MLBEDSW-7074: Updated reference kernel for the MEAN opJohan Alfvén
The reference kernel for the MEAN operator has changed. As a result, the mean implementation can be simplified and the constraint for mean int8 can be removed. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I318e9b495eefea99e7ac4aea4b8c436c83753405
2022-10-28MLBEDSW-6975: Updated bypass functionalityJohan Alfvén
- The previous patch the always replaced ifm with ofm introduced unnecessary avg pool ops for some cases. That patch has been reverted and this is a new solution. - Replace ifm with ofm for the following condition: a) Ops that are dependent that the original ifm tensor shape is not changed by the bypass memory op function. b) When the memory op has different IFM and OFM rank. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I16a023e169ae64c5db46f6f88516a5e1ca7ed7ef
2022-10-28Revert "MLBEDSW-6961: Bypass functionality for memory ops"Johan Alfvén
This reverts commit 5060ff53f5ac2382e04a68d7772bd71a36f63845. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I8dd7e9ed8325fd2e8c17509fd9757292706f5ee7
2022-10-19MLBEDSW-7020: TRANSPOSE_CONV stride documentation is confusingTim Hall
- The op contained supported operator checks for both the stride being in the range 1 to 3, and being equal to 2. Whilst both are correct, only the later is needed - Removed the stride in the range 1 to 3 check for TRANSPOSE_CONV - Regenerated the documentation Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I9789cdbd3ed65ce310f1529036abbac62296d2ca
2022-10-18MLBEDSW-6794: ResizeNearestNeighbor with HPCJohan Alfvén
- Removed half pixel centers constraint for resize nearest neightbor. - Supported scale 2x, 4x and 8x. - Removed test_constraint_resize_half_pixel_centers - Regenerated SUPPORTED_OPS.md Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: Ic3e02e9c2b2034d537c9a9841b8fb4ee433c96dc
2022-09-27MLBEDSW-6961: Bypass functionality for memory opsJohan Alfvén
- In order to solve output diffs, the Reshape op was pushed to the CPU. The problem was that the Mean op ifm shape was replaced by the Reshape op ifm shape. - This limitation is now removed. Changed implementation how memory only ops are bypassed. Always replace the memory only op ifm tensor with its ofm tensor. By doing this the ifm tensor for the operator that is after the memory only op is never changed. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: Ibcdebf33fd9b7a37f90984a129500b5dac52e5ea
2022-09-26MLBEDSW-4075 PACK axis 0 + tanh fails with output diffFredrik Svedberg
The test failed since the tanh had batch size > 1. Added checks for batch size for all supported operators. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I3570352740c40eb96bd9db965dfa3c91c81ff2ad
2022-09-26MLBEDSW-6932 LeakyRelu missing from supported ops activationsFredrik Svedberg
Added LeakyRelu to supported activation ops. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: Icca27730946d02ec16159f988782567be716b594
2022-09-23MLBEDSW-6928: Add int16 support for Resize Bilinear HPCRickard Bolin
Setting bias tensor dtype to DataType.int32 solves rounding issues for RB HPC int16. Removing the input data type check also solves the issue of resize nearest neighbor int16 ops incorrectly getting placed on the CPU. Signed-off-by: Rickard Bolin <rickard.bolin@arm.com> Change-Id: Iee352bcb78e581c0cde3c203dfbe866f1f6fae18
2022-09-23MLBEDSW-6686: Resize bilinear HPC with tile paddingRickard Bolin
- Added support for Resize Bilinear with half pixel centers for int8 and uint8. - Utilizes the new "TILE" padding mode. - Utilizes ofm stride multipliers and modified tile base offsets to write OFMs interleaved. Signed-off-by: Rickard Bolin <rickard.bolin@arm.com> Change-Id: I37fa77c022a368f05fda0ead75d8696c9205f833
2022-09-12MLBEDSW-6863: Cleanup the constraint for concatJohan Alfvén
Removed duplicate code and moved constraint to the correct file. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I2da3c5b88e1af351751c481217b8183b5948f0f8
2022-09-12MLBEDSW-6909: Use int32 acc for the Mean opJohan Alfvén
Changed acc type from int16 to int32. This will solve saturation problems and the constraint added in commit "MLBEDSW-5029: Output diff for Mean op" can be removed. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I05ec8835b43313b1a264d61a2b147fa62da123fe
2022-09-01MLBEDSW-5029: Output diff for Mean opJohan Alfvén
Fixed three test cases causing output diff compared to the reference kernel for the Mean operator. - If there is a possibility that the accumulator could saturate the Mean op must run CPU - Use correct rounding for the bias term - If a Reshape op is followed by a Mean op, push the Reshape op to the CPU since this cannot be handled by the NPU Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I734465730372105821a5e2f73a6a125b9eb7d7f4
2022-08-31MLBEDSW-6832 PReLU support in VelaFredrik Svedberg
Added PReLU support in graph optimiser. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I3a188675e3edcdf0b4a4bfcdd134fda0bf8a560f
2022-08-17MLBEDSW-6830: MLCE: Fix assert on concat opJohan Alfvén
- The compiler will assert when compiling a faulty concat op. In the reported use case, there were 3 inputs with shape 1x1x2 but the output shape was 1x1x2 (expected to be 1x1x6) - The solution is to add constraints to the concat operator. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I94a505c51a9fd54d1aa92531a0415031db52378a
2022-07-23MLBEDSW-4157: Add RESIZE_NEAREST_NEIGHBOR supportTim Hall
- Changed ResizeBilinear to support ResizeNearestNeighbor as well for 1x1 IFM, IFM equal OFM, and non-align corners - Added support for ResizeNearestNeighbor with align corners by converting to a DepthwiseConv - Updated supported operator unit tests - Added is_resize() helper function and some associated refactoring Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Id5bdf2a25e8aa6a4f28b7236250abf768141ce37
2022-07-23MLBEDSW-6616: ResizeBilinear align corners is incorrectTim Hall
- Fixed align corners support when converting in to upscale and average pool. The problem was due to the wrong ratio ifm to ofm size, causing an scaling factor that was not 2x/4x/8x. Works for uint8, int8 and int16. - Fixed checking of align corners in supported operators check - Added additional supported operators check for the size tensor - Updated and added more supported operators unit tests Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Idb78fa9e76ede2c37e8ac6cb1c322154bd156898
2022-07-15MLBEDSW-6703 Add SHAPE operator to supported operatorsFredrik Svedberg
Added SHAPE operator to the supported operators report. Updated the constraints for QUANTIZE and SHAPE operator. Also fixed RESHAPE consuming statically optimised shape. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I1d964d602d3f361a0f16dae8133197280dd84c48
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