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path: root/ethosu/vela/supported_operators.py
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2020-09-28MLBEDSW-2885: Fix overflow from inf numberAndreas Nevalainen
Added check for inf numbers for all scales. Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: I84fcae429be4869d8489f66bef26863c254104cd
2020-09-28MLBEDSW-3035: Updated StridedSlice checksLouis Verhaard
Updated supported operator checks for StridedSlice: - allow negative indices in begin/end values - added more checks on shapes Change-Id: I3ac76bfa6b313f0e2250f0749f152fb0e3aa033c Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-24MLBEDSW-2788 Fix crash on non-constant weight tensorsAndreas Nevalainen
Change-Id: I750ec63a0e37b38feaf4cbdcc883fdbef92bccdf Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
2020-09-22MLBEDSW-2813: Handle non-const weights and check shapesAndreas Nevalainen
- Added check for non-constant weights in supported operators - Added check ifm & ifm2 shapes - Handle None tensors for CPU operators - Handle missing attributes for Cast operator Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: I2f16d3d44d0c6da5237550b39273cdb9cc3c7607
2020-09-08optim: Fix issue with IFM streaming of LUTMichael McGeagh
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I3c3ed73a6db39615ddf5987dc5696b6b09682be0
2020-09-07[MLBEDSW-2928] Add batching to softmaxFredrik Svedberg
Added batching to softmax by reshaping the input. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I0b516f9bf2410fb86372b229beba4a7280c498cc
2020-09-03MLBEDSW-2814 Add support for inferred size in SplitVPatrik Gustavsson
For SplitV sizesplit can contain one -1 indicating that dimension is to be inferred. Support added to handle this. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ib9fc8dd2ee1749e81a978d85f2d4a016698bb441
2020-08-31MLBEDSW-2915: Added None check for bias before checking restrictionsJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I04618fd0d29075e7d3f8f27a320129603f045163
2020-08-29MLBEDSW-2804: Bias data type check wrongTim Hall
- Fixed bias check to use quantised values. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I6d87439938b9b5aeec87814e5a30d59fd06d5748
2020-08-28MLBEDSW-2804: Added bias data type checkJacob Bohlin
Allows int64 data type to be used as long as all values can be packed into a int40 value. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I0e25ec482e3ea765a5fd00bcf7e212a9e65a1461
2020-08-27[MLBEDSW-2846] Do not use NHCWB16 for reduce_sum int32Fredrik Svedberg
Added checks for not using NHCWB16 for reduce_sum int32 which makes int8/uint8 softmax work. Also enabled softmax graph rewrite by default and fixed a saturation problem. Change-Id: Ic01bd9ece7e5c3edb2900b7915cc747efe9e5760 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-08-27MLBEDSW-2719: Update kernel size checkAndreas Nevalainen
Updated kernel size check, width and height was swapped and added weight sum check. Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: Idb18cf258ac19b3a0d71134dab5a117bcd778b59
2020-08-25MLBEDSW-2867: Split operators get placed on CPUDwight Lidman
This commit fixes a bug wherein Split operators are being erroneously placed on the CPU due to a 0-dimensional input that disqualifies it from NPU placement; a restriction introduced in a recent commit. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I83c047ddf071d662343087c69bdb2a014dd209c3
2020-08-24MLBEDSW-2654: Convert Resizebilinear to a number of 2x2 poolsCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: Ida307afc33cd7963bdeb505df400732a3efcc846
2020-08-21MLBEDSW-2679: Tensor quant comparison is incorrectTim Hall
- Fixed bug with the supported operator check rejecting operators based upon an incorrect comparison of the tensor quantisations Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ibd0eb50077465d2c515c6ee10394d9b43cdf730c
2020-08-21MLBEDSW-2663: Handle optional tensorsJacob Bohlin
Includes a number of changes: * Handle non-existing optional inputs * Handle disabled optional inputs (-1 indexed) * Added unit tests for parsing operators * Add bias tensor to the different Convolutions + FullyConnected if it's missing. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: Ib88d2b610314b1c886fc0aef4f9da87430ce6ae5
2020-08-21[MLBEDSW-2730] Implement LUT generation for softmax uint8/int8Fredrik Svedberg
Implemented LUT generation for softmax uint8/int8 to match the reference. Change-Id: Ib9acaa295ee1066591e800023d75f364520b44c1 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-08-19MLBEDSW-2729: Add restrictions for shapeless tensorsDwight Lidman
Vela often fails when encountering operators that have inputs or outputs with shape == []. Only for elementwise ops where shape is broadcasted from IFM2 to IFM1 is this supported. This commit adds a restriction which places ops with shape [] tensors on the CPU except in the special case of broadcasting for elemwise ops. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I5b0855233e3b83870209f4da00fb2dbd0184fee0
2020-08-19[MLBEDSW-2657] Softmax uint8/int8Fredrik Svedberg
Added graph rewrite of Softmax for uint8/int8. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: Iecdd5d2cd3156a601b3313debba4a3562e6be5d7
2020-08-06MLBEDSW-2549 Crash with incorrect strided slice opMichael McGeagh
A valid strided slice should have (positive) non-zero elements when you do "end - begin" When encountering an invalid strided slice, vela asserted. This now checks that it is valid and wont claim support if it isnt. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I33ef118bd6a31ac78c680acb5229ff31b0809d6a
2020-08-06Skip the NOP resizebilinear opCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: Ibd0cd152fbc46dea0c92fd1bf7da1ffc9803fdba
2020-08-05[MLBEDSW-2335] SoftMax int16Fredrik Svedberg
Added graph rewrite of Softmax for int16. Change-Id: Id7885af6056a23e8b8362fb61ae94283251eb398 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-08-05MLBEDSW-2569:Support 1x1 IFM ResizeBilinearCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: I44428d77b2e8e44a477e5c4dfe28ab8dd1792838
2020-07-14MLBEDSW-1538: Output diff for elementwise min/maxDwight Lidman
This commit adds a quantization restriction check for supported operators, so that operators with different quantization between its IFM (1/2) and OFM tensors that do not support it, are correctly placed on the CPU. The quantization between two tensors is compared using a new equality function implemented for the QuantizationParameters class. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I70ff36b4ab4955f328d6e6e699f00dbc43c0404a
2020-07-10MLBEDSW-1497: Add Quantize operator supportJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: Iaf4d7ab9c32b0d783072c5f131a61bfebe77cc16
2020-06-18Code clean-up using black and flake8Tim Hall
- No functional change Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I5ab1198b9d092cd041fa9b85b2dee9900d299bfc
2020-06-18MLBEDSW-2475: leaky relu not handling negative alpha valueDwight Lidman
This commit places LeakyReLU operators with a negative alpha value on the CPU and avoids a crash during command stream generation. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Iac68c5a9fdbf26facb709660965615b2b5b551f9
2020-06-18MLBEDSW-1716: Transpose Convolution supportJacob Bohlin
Change-Id: Ie6d8d6de9f3447f19ba06aafa9fa480fc96a973b Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
2020-06-18MLBEDSW-2372: Failing assert for ResizeBilinear with upscale != 2xDwight Lidman
This commit fixes the failing assert by removing it and instead placing unsupported ResizeBilinear operators on the CPU. It introduces a new graph optimisation function which adds the necessary attributes as well as new operator restrictions for ResizeBilinear. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I2feffd0b5a2169ebffbe4f165e450b3f2d140380
2020-06-18[MLBEDSW-1996] Update supported operator checksFredrik Svedberg
Updated supported operator checks according to latest requirements. Change-Id: I79708d8039e464e39818d3c09e61f3f533e96f3d Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-06-18Add elementwise vector scalars supportCharles Xu
Write the constant scalars into flash. In case it's Dram or OffChipFlash, DMA the scalars from flash to sram. Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: I42300a05dfe968d623b8aec8549644549e0f54b5
2020-06-18MLBEDSW-1649: Add size splits for Split opCharles Xu
The tensor is split into len(size_splits) along the dimension axis with the sizes specified in the size_splits array. Change-Id: I2ce98fa10e2e26f16cfd86a775aee94a308509ea Signed-off-by: Charles Xu <charles.xu@arm.com>
2020-06-18Add reorder-python-import pre-commit hookDiego Russo
Also updated README.md Change-Id: I118309c61f4d00e8508d6b888c606995490fba39 Signed-off-by: Diego Russo <diego.russo@arm.com>
2020-06-18MLBEDSW-1498: Add Resize_Bilinear operator supportDwight Lidman
This patch adds support for the ResizeBilinear operator. It is implemented using a 2x2 Nearest Neighbor upscale followed by a 2x2 Average Pool. Depending on the argument align_corners the output is either of shape: - (2 * M, 2 * N) when align_corners == True, or - (2 * M - 1, 2 * N - 1) when align_corners == False where (M, N) is the input shape. The padding mode is SAME when align_corners == True and VALID when align_corners == False. The argument half_pixel_centers is out of scope and is as of now ignored. Note that only upscaling by a factor of 2 is supported. Change-Id: Ia6d6d010c4f1bb13f5f839bc8d16872a626d9a3b Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
2020-06-18MLBEDSW-1998: Add support for new_axis_maskPatrik Gustavsson
-Added support for new_axis_mask -Added support for more than 1 bit set in new/shrink_axis mask -Added checks for strided slice in supported operator check -Added assert if nothing has been put on NPU Change-Id: I66e2d04784f14d7ad82371f5d649a455d576a818 Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
2020-06-18MLBEDSW-1970: Add stride 3 supportDwight Lidman
This patch adds support for strides of size 3. It removes some obsolete code for a corner case that no longer exists. It also changes the setting of the bitfield in NPU_SET_KERNEL_STRIDE so that it matches the specification. Change-Id: I7dabcf72b7826ca0b3c98e9d23209027204079a8 Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
2020-06-18MLBEDSW-2001: Fix unary elementwise operator regressionDwight Lidman
Change-Id: I8f109cd148aaa17c18a97068fad52419c8d9d12e Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
2020-04-29Add Vela codebase0.1.0Tim Hall
- Added modules ethosu.vela and ethosu.mlw_codec. - Added README and various configuration files. Change-Id: I3690f8c8f5966306ecddaeb2793c30ca9c6e2eee
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