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Enables LUT for LeakyRelu with int8/uint8 even if input scale
is different from the output scale.
Fusing LUT with a previous operator for this situation
requires further work.
Change-Id: I9eddfe36f457e763d44eb3e05fbe240eac7cfec9
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I287c24725126c169afec779b921e43c3ab26f739
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For int16, using LeakyRelu (with bug fix) gives exactly
the same results as Mul+Max if input/output scales are the same.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I4f4db464d77b0aaf0d25ddfca534f91d08db548d
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Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I2cb3f6639e4bb8a984fa3647ee7b4678ed6f5890
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Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: Ida307afc33cd7963bdeb505df400732a3efcc846
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Replaces LeakyRelu operations with LUT activation function when possible,
else to a combination of multiplication/maximization.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I3d2eb2dba7145997c3cc711d0ef18ab355fbb416
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Includes a number of changes:
* Handle non-existing optional inputs
* Handle disabled optional inputs (-1 indexed)
* Added unit tests for parsing operators
* Add bias tensor to the different Convolutions + FullyConnected if
it's missing.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: Ib88d2b610314b1c886fc0aef4f9da87430ce6ae5
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NHCWB16 is avoided for the input tensor for SplitSliceRead,
when any of the consumers has an start offset in C-dimension
that is not a multiple of 16.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I333e2acfbeb02b9c34ee5ea28074baff12ea7b24
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4 dimensions where assumed in check if NHCWB16 should be avoided.
Changed check so that if axis corresponds to C-dimension,
NHCWB16 should be avoided.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I7784a7a813a3c3438d6142523bf0a3ba81742aca
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Avoid usage of NHCWB16 when Stack/Pack/Concat is performed in axis 3,
and the "concat start" of each slice to be combined is not a multiple
of 16.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: If3f7b4a3424be3c86fc2dc48e8649ce4c4f49485
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add_input_tensor, set_output_tensor, create_const_tensor and
create_reshape_tensor have recently been added.
This replaces all found existing instances with these new helper
functions
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: If33be8dbf237b2087b562b03cdeb51da1f99a786
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Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: Ibd0cd152fbc46dea0c92fd1bf7da1ffc9803fdba
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Added graph rewrite of Softmax for int16.
Change-Id: Id7885af6056a23e8b8362fb61ae94283251eb398
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I44428d77b2e8e44a477e5c4dfe28ab8dd1792838
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By converting certain Conv2D's (where the kernel size is 1x1 and the
IFM H and W are both 1) to Fully Connected's, vela can better know
whether the weights need to be cached/double buffered or not.
This change decreases the number of NPU_OP_DMA_START commands found in
the resulting command stream.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: I928150d9f360578dde75a83986bea1560d83cbdd
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There is a repeating pattern of setting the 3 different shapes in a
tensor to a single shape value.
This adds a new function in the tensor class that does this for you.
Changed existing instances of manually setting shape to use this new
function.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: Ibc74e741ea47cec473e6be42cc102f721ec63b11
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Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I39cff126dda89d71426ab731427ca1d64d02590d
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This will give a worst case estimate of the Double Buffer size in the
Scheduler and it will no longer be able to choose strategies that end
up with a buffer that doesn't fit in SRAM.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I763731f63c7672679f3b8cd6db65dad03b946ae5
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- No functional change
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I5ab1198b9d092cd041fa9b85b2dee9900d299bfc
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Tensors that are the result of an operation were incorrectly marked
as scalars.
Also fixes a bug for IFM2 of shape [*,*,*,1] in elementwise operations.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I82a0e643b12e93c7158e4aca3185415c59033a73
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Change-Id: Ie6d8d6de9f3447f19ba06aafa9fa480fc96a973b
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
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- Dilation added to SET_KERNEL_STRIDE instruction
- Kernel height/width adjusted for dilation
- Updated padding calculation
- Updated weight compression
Change-Id: I0c8190223e223b039a305aba0f37896ae1de2b80
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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This commit fixes the failing assert by removing it
and instead placing unsupported ResizeBilinear
operators on the CPU.
It introduces a new graph optimisation function
which adds the necessary attributes as well as
new operator restrictions for ResizeBilinear.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I2feffd0b5a2169ebffbe4f165e450b3f2d140380
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Added custom exceptions to handle different types of input errors.
Also performed minor formatting changes using flake8/black.
Change-Id: Ie5b05361507d5e569aff045757aec0a4a755ae98
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Write the constant scalars into flash. In case it's Dram
or OffChipFlash, DMA the scalars from flash to sram.
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I42300a05dfe968d623b8aec8549644549e0f54b5
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- Pack and reshape operators were manipulating tensors of
different equivalence IDs that refer to the same memory
area, causing issues with block dependency checking.
Ideally we'd use address overlap calculations for accuracy,
but this commit implements a generalised solution by
setting memory op IO tensors to use the same equivalence ID.
Change-Id: Ia59ae3900f508ffeebaf7af4bca32f5be4e69345
Signed-off-by: Tim Hall <tim.hall@arm.com>
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Also updated README.md
Change-Id: I118309c61f4d00e8508d6b888c606995490fba39
Signed-off-by: Diego Russo <diego.russo@arm.com>
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This patch adds support for the ResizeBilinear operator.
It is implemented using a 2x2 Nearest Neighbor upscale
followed by a 2x2 Average Pool.
Depending on the argument align_corners
the output is either of shape:
- (2 * M, 2 * N) when align_corners == True, or
- (2 * M - 1, 2 * N - 1) when align_corners == False
where (M, N) is the input shape.
The padding mode is SAME when align_corners == True
and VALID when align_corners == False.
The argument half_pixel_centers is out of scope and is
as of now ignored.
Note that only upscaling by a factor of 2 is supported.
Change-Id: Ia6d6d010c4f1bb13f5f839bc8d16872a626d9a3b
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
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Use pre-commit framework [1] to run black and flake8 before the commit.
black and flake8 are managed by the pre-commit framework and they can be
run manually by the user using `pre-commit run` command.
Fix the code base with the help of black and flake8.
Fix import statements according to PEP8 guidelines [1]
Both tools have the following settings (specified in the pre-commit
configuration file):
* line length: 120 characters
* directory to exclude: ethosu/vela/tflite/ and ethosu/vela/ethos_u55_regs
Updated README.md on how to install pre-commit and how to run sanity checks.
Pipenv files have been updated including new dependencies for pre-commit.
[1]: https://www.python.org/dev/peps/pep-0008/#imports
[2]: https://github.com/pre-commit/pre-commit
Change-Id: I304d9fffdf019d390ffa396a529c8a7c2437f63d
Signed-off-by: Diego Russo <diego.russo@arm.com>
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-Added support for new_axis_mask
-Added support for more than 1 bit set in new/shrink_axis mask
-Added checks for strided slice in supported operator check
-Added assert if nothing has been put on NPU
Change-Id: I66e2d04784f14d7ad82371f5d649a455d576a818
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
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- Added modules ethosu.vela and ethosu.mlw_codec.
- Added README and various configuration files.
Change-Id: I3690f8c8f5966306ecddaeb2793c30ca9c6e2eee
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