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2020-11-20Revert "MLMBED-3450: Do not convert batched fully connected to conv"2.0.0.rc2Patrik Gustavsson
This reverts commit 15a8e803844b286fe9533e1cf703c76a77b090a8. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I64169443f473c9ba42551281ad6ac4b45856f420
2020-11-20vela: Tanh and Sigmoid broken in fixup_act_reorderTim Hall
- Fixed bug due to typo in Op.type refactor Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I55916d90bf792648f496a45c358b7e897c6730ba
2020-11-20vela: Improve the scaling is equal checkTim Hall
- Improved tensor and scaling query functions - Fixed bug in convert_batched_fc_to_conv Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ibc3d14036540f27cf5e993beb2163d3e0f5e5933
2020-11-17MLMBED-3450: Do not convert batched fully connected to convAndreas Nevalainen
Do not convert batched fully connected operators to avoid moving weights from flash to SRAM. Change-Id: I873c9ce05377de3f16e4cee9a0863f29d9ec3ad4 Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
2020-11-13MLBEDSW-839: Code generation using external API2.0.0.rc1Louis Verhaard
Added external API to generate register command streams. Existing code generation has been refactored to make use of this API. Change-Id: Ibb4c2b167809869f16470b14da24f08a65c82b7b Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-11-11MLBEDSW-3463: StridedSlice fixup function causes infinite recursionDwight Lidman
This commit reverts a control flow path where already modified StridedSlice operators are left untouched. If not, Vela would recurse infinitely and crash. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Iaf3ae916325bedd3dd1edd3395fb4a9ecf832590
2020-11-11MLBEDSW-3019: Add profiling debug databaseTim Hall
- Added mechanism to track input to output graph transforms for debugging the resultant command stream. - Provides base implementation for MLBEDSW-2661 Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I2dfe8a409fbde7ad0282bfab5acb11ba1c8b82d8
2020-11-10MLBEDSW-3377: fixup_stridedslice_output may silently change CPU opsDwight Lidman
This commit removes the constraint on all tensor shapes matching the OFM shape. The motivation is that this constraint essentially only checks that the fixup function has run. This means that it removes the possibility for the fixup function to run after the supported operator check and this effectively means that any StridedSlice operator that would be placed on the CPU is still modified by the fixup function. Because the fixup function is moved to after the supported operators check, some unreachable cases are removed from the fixup function. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I7a82126b7de73bd67873b4e6daf53a6767e33d16
2020-10-26MLBEDSW-3283: Bug fix: StridedSlice Op is placed on CPUDiqing Zhong
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com> Change-Id: I91a3b277cda91dca3bad38908d4ed11a4f5d7d5f
2020-10-21vela: Improve the scaling is equal checkTim Hall
- Fixed and documented both tensor and quant params scaling checks - Added quant params validity check and tensor quantisation check - Added valid tensor checks to some graph optimisation functions Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I8d6e8f03a603d28886dde511672c8399c85b794c
2020-10-16MLBEDSW-3004: UnpackReshaped can't be serialisedDwight Lidman
This commit fixes a bug where a rewritten Unpack operator is placed on the CPU and crashes Vela during serialisation due to the type having changed and there not being a mapping for the modified op type. The solution is to move the fixup_unpack_output function to the graph optimisation pass B, allowing the supported op check to run before it. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ic6bd4c70a478fd61adf377cb487f5b9253130314
2020-10-12MLBEDSW-3154 Bug fix for LUT ops with IFM from SplitSliceReadLouis Verhaard
- Incorrect length check in high level command stream generator - Improved tensor names related to LUT based operations Change-Id: Ib8844a35a986e2dbef095df23f143f4633b255f9 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-08MLBEDSW-3148: Refactor OperationLouis Verhaard
- op.type is now an enum instead of a string - Removed unused operator codes - Refactored some attributes like npu_block_type, fused_activation_function - Refactored operator index calculation - Refactored a number of operator sets Change-Id: I641f65ee375794b7aec42abc0664251ae37d78e8 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-02MLBEDSW-3060 Adjust check if weights fit in sramPatrik Gustavsson
When deciding if weights fit sram: A compression of the weights has been added when a weight compression test limit makes it impossible to fit weights in a double buffer in sram. The worst compression ratio from compression, is used to decide if weights can be fit in sram. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I9458769866b3f9fc15659185aae09658ed10fb38
2020-09-30MLBEDSW-3153: Fix overflow in sigmoid LUTLouis Verhaard
Overflow could occur in the calculation of the LUT table for sigmoid, for big negative inputs. Change-Id: I62a33c68de03e9a7a7e4fe2cbd5835c384dc3643 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-30[MLBEDSW-2802] Fix 5D tensor crashFredrik Svedberg
Fixed crash in networks with 5D tensors. Fixed crash for (int32) tensors without quantization. Added validity checks for concatenation. Moved unfusing of activation function from tflite_reader to graph_optimiser. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: Ib9ba8891dc95ef5491e15d0feedef44331a26393
2020-09-29MLBEDSW-3032 Fixed issue in removal of reshapesPatrik Gustavsson
Fixed issue in removal of reshapes Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Id6081de8d6b7b6815cc5e56881c20e075214c407
2020-09-29MLBEDSW-2031: LUT support tanh/sigmoidLouis Verhaard
Uses LUT for int8/uint8 based tanh/sigmoid. Change-Id: Ib6ac5a5c958ab9a17e47f620b22c3e22d8d60321 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-25MLBEDSW-2811: Add rescaling to ReLus with different scalingAndreas Nevalainen
If IFM/OFM is not 4d rescaling ops are added to ReLus with different scaling. Change-Id: I631d44fc8a51fb476b9f62ef90eda26eef3d35f3 Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
2020-09-23MLBEDSW-3018 Change to check for avoiding NHCWB16Patrik Gustavsson
Fixed issue with checking if axis corresponds to C-dim Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I72d9fd2c9fca642b5ab326324a63111b01c5de98
2020-09-21MLBEDSW-1693 Convert batched FC to ConvPatrik Gustavsson
Added support to convert batched FC to conv. This enables choosing a suitable block-size. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Idc49e4fb6d29c554f10a38ece7996a7b7795ffad
2020-09-17MLBEDSW-3008: Replace Split ops with IdentityDwight Lidman
A Split operation with num_splits=1 is essentially a NOP. This commit adds a graph optimisation function which replaces said Split ops with an Identity op for later pruning. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I0b0c535f214f54ee4c255662a18c37543bdc6d64
2020-09-11MLBEDSW-2745 Support relus with differing scalesMichael McGeagh
In the event we have a relu op with different input and output scales, we need to fuse it with a nop avgpool. Also refactor the existing avgpool nop code to a common function. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Iedf4513e7595ee4ee1777ba0b1eb38a8df8aed5e
2020-09-11MLBEDSW-2994 Remove undesired reshape OPsPatrik Gustavsson
Addded functionality for removing reshape OPs, that enclose an Elementwize OP with only one non-constant Tensor. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Idaac50cfbd732e2667668be2baa059673236cc56
2020-09-08vela: Refactor op sets in graph_optimiserMichael McGeagh
We have a number of sets for grouping specific ops together but arent used that much in code. This updates the file to better utilise these sets. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I719212671f8bdebc32576278f703549f0937ff65
2020-09-08MLBEDSW-2935: LUT fusing with preceding operatorLouis Verhaard
Allows fusing of LUT with a preceding operator regardless of input/output scale. Change-Id: Ia378adbb3fe61d71299feb085f7313377e0efa39 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-03MLBEDSW-2906: Only add padding fields to Npu opsJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I75aad9bf59ad76ee6a0c0feb4d7299b50d787fe8
2020-08-28MLBEDSW-2688: LUT calculation with different in/out scaleLouis Verhaard
Enables LUT for LeakyRelu with int8/uint8 even if input scale is different from the output scale. Fusing LUT with a previous operator for this situation requires further work. Change-Id: I9eddfe36f457e763d44eb3e05fbe240eac7cfec9 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-08-27Small fix for Softmax regressionJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I287c24725126c169afec779b921e43c3ab26f739
2020-08-26MLBEDSW-2688: use LeakyRelu for int16Louis Verhaard
For int16, using LeakyRelu (with bug fix) gives exactly the same results as Mul+Max if input/output scales are the same. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I4f4db464d77b0aaf0d25ddfca534f91d08db548d
2020-08-26MLBEDSW-2847: Fix for TransposeConv crash and u8 output diffJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I2cb3f6639e4bb8a984fa3647ee7b4678ed6f5890
2020-08-24MLBEDSW-2654: Convert Resizebilinear to a number of 2x2 poolsCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: Ida307afc33cd7963bdeb505df400732a3efcc846
2020-08-24MLBEDSW-2688: LeakyRelu rewrite to LUT or MUL/MAXLouis Verhaard
Replaces LeakyRelu operations with LUT activation function when possible, else to a combination of multiplication/maximization. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I3d2eb2dba7145997c3cc711d0ef18ab355fbb416
2020-08-21MLBEDSW-2663: Handle optional tensorsJacob Bohlin
Includes a number of changes: * Handle non-existing optional inputs * Handle disabled optional inputs (-1 indexed) * Added unit tests for parsing operators * Add bias tensor to the different Convolutions + FullyConnected if it's missing. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: Ib88d2b610314b1c886fc0aef4f9da87430ce6ae5
2020-08-19MLBEDSW-2779 Avoid NHCWB16 in some SplitSliceRead casesPatrik Gustavsson
NHCWB16 is avoided for the input tensor for SplitSliceRead, when any of the consumers has an start offset in C-dimension that is not a multiple of 16. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I333e2acfbeb02b9c34ee5ea28074baff12ea7b24
2020-08-18MLBEDSW-2779 Consider num dimensions, in check for NHCWB16Patrik Gustavsson
4 dimensions where assumed in check if NHCWB16 should be avoided. Changed check so that if axis corresponds to C-dimension, NHCWB16 should be avoided. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I7784a7a813a3c3438d6142523bf0a3ba81742aca
2020-08-14MLBEDSW-2570 Avoid usage of NHCWB16 for some casesPatrik Gustavsson
Avoid usage of NHCWB16 when Stack/Pack/Concat is performed in axis 3, and the "concat start" of each slice to be combined is not a multiple of 16. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: If3f7b4a3424be3c86fc2dc48e8649ce4c4f49485
2020-08-12MLBEDSW-2637 Utilise new tensor and operator funcsMichael McGeagh
add_input_tensor, set_output_tensor, create_const_tensor and create_reshape_tensor have recently been added. This replaces all found existing instances with these new helper functions Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: If33be8dbf237b2087b562b03cdeb51da1f99a786
2020-08-06Skip the NOP resizebilinear opCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: Ibd0cd152fbc46dea0c92fd1bf7da1ffc9803fdba
2020-08-05[MLBEDSW-2335] SoftMax int16Fredrik Svedberg
Added graph rewrite of Softmax for int16. Change-Id: Id7885af6056a23e8b8362fb61ae94283251eb398 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-08-05MLBEDSW-2569:Support 1x1 IFM ResizeBilinearCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: I44428d77b2e8e44a477e5c4dfe28ab8dd1792838
2020-07-30MLBEDSW-2660 Convert FC-like convs to FCMichael McGeagh
By converting certain Conv2D's (where the kernel size is 1x1 and the IFM H and W are both 1) to Fully Connected's, vela can better know whether the weights need to be cached/double buffered or not. This change decreases the number of NPU_OP_DMA_START commands found in the resulting command stream. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I928150d9f360578dde75a83986bea1560d83cbdd
2020-07-30vela: Move common functionalityMichael McGeagh
There is a repeating pattern of setting the 3 different shapes in a tensor to a single shape value. This adds a new function in the tensor class that does this for you. Changed existing instances of manually setting shape to use this new function. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Ibc74e741ea47cec473e6be42cc102f721ec63b11
2020-07-13MLBEDSW-2584: Support cascading of Transpose ConvolutionJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I39cff126dda89d71426ab731427ca1d64d02590d
2020-07-07MLBEDSW-2548: Fix for Double Buffer size estimateJacob Bohlin
This will give a worst case estimate of the Double Buffer size in the Scheduler and it will no longer be able to choose strategies that end up with a buffer that doesn't fit in SRAM. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I763731f63c7672679f3b8cd6db65dad03b946ae5
2020-06-18Code clean-up using black and flake8Tim Hall
- No functional change Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I5ab1198b9d092cd041fa9b85b2dee9900d299bfc
2020-06-18MLBEDSW-2379: Fix 1-element tensors that were marked as scalarsLouis Verhaard
Tensors that are the result of an operation were incorrectly marked as scalars. Also fixes a bug for IFM2 of shape [*,*,*,1] in elementwise operations. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I82a0e643b12e93c7158e4aca3185415c59033a73
2020-06-18MLBEDSW-1716: Transpose Convolution supportJacob Bohlin
Change-Id: Ie6d8d6de9f3447f19ba06aafa9fa480fc96a973b Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
2020-06-18MLBEDSW-2420: Improved support for dilated convolutionLouis Verhaard
- Dilation added to SET_KERNEL_STRIDE instruction - Kernel height/width adjusted for dilation - Updated padding calculation - Updated weight compression Change-Id: I0c8190223e223b039a305aba0f37896ae1de2b80 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-06-18MLBEDSW-2372: Failing assert for ResizeBilinear with upscale != 2xDwight Lidman
This commit fixes the failing assert by removing it and instead placing unsupported ResizeBilinear operators on the CPU. It introduces a new graph optimisation function which adds the necessary attributes as well as new operator restrictions for ResizeBilinear. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I2feffd0b5a2169ebffbe4f165e450b3f2d140380
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