Age | Commit message (Collapse) | Author |
|
Keeping the constraint functions consistent with each other
Added specific tensor names in the extra info
Added operator name to the warning generated
This should help easily identify specific problematic nodes in a graph
and give a good enough explanation as to why they are placed on the CPU
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: Ie5bbdd31e5e75fe37e3d8bb8fee1d260080bce83
|
|
Added info print for unsupported operator
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I1002d1c2249661bff17ef86d9500d1aeb2a1e38e
|
|
Vela supports batching of FC, restriction removed.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ica56738f1b2676628644fc44f2039a24807f5ccb
|
|
Vela could crash in operator serialization if "fused_activation_function"
was not set.
Change-Id: I7f2364b0849fd371dee87e26c6d33d44ce8cec26
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
- Incorrect length check in high level command stream generator
- Improved tensor names related to LUT based operations
Change-Id: Ib8844a35a986e2dbef095df23f143f4633b255f9
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
This commit changes and amends some parts of the
restriction functions in order to make sure
operators are correctly placed.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I336cf33a874c9078a5bbf81ce129ff917dbc5e9a
|
|
Change-Id: Idcf1665f95ddecc2a12ff0e714f645263981d501
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
Added check so that inputs with no values are not reshaped.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Id5e53b093508583c2d70ba7e337869db3de32701
|
|
- op.type is now an enum instead of a string
- Removed unused operator codes
- Refactored some attributes like npu_block_type, fused_activation_function
- Refactored operator index calculation
- Refactored a number of operator sets
Change-Id: I641f65ee375794b7aec42abc0664251ae37d78e8
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
Fix issue for checking axis in concat, now allowing 0.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I85a5fc3dacdfc66dc01b0e05048dd100254fddff
|
|
The latest "stable" version of Black formats code
differently from the 19.10b0 version that has been
used in the past, which introduces unwelcome
formatting changes in newer commits.
This commit explicitly sets the revision to
19.10b0.
It also changes the repo parameter to point to the
new URL.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I20c73f0c87434143f62282f5f0399f73cedfd6ce
|
|
- Presence of accumulators in validation was preventing some elementwise
configurations from being chosen. This commit sets accumulator requirement
to zero before validating the shared buffer config.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Id79f80afb12f77274ade53f7678c3b2e56aef059
|
|
A new mechanism to report generic restrictions/constraints for
operators has been implemented.
Each check is its own defined function, and has a general reason for
the constraint defined as its docstring.
This allows us to query all reasons up front and report this without
having to run through real data to trigger the checks.
This is part of a larger refactoring and the specific restrictions will
be replaced by a similar mechanism.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: Id3fb2639f91cfac5fc5b8c14f7620de1a85972b2
|
|
Part of larger refactoring. The sets of operators do not need to be
instance attributes and are not expected to be modified at runtime.
This in turn allows almost all functions to become class methods.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: I7dc24d65cdd6c4bda641b3d6133b3134302a552f
|
|
Issues should be reported via arm-security@arm.com
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Iea06e77dbabedcbe334dd63f644b63ec737f82df
|
|
When deciding if weights fit sram:
A compression of the weights has been added when a
weight compression test limit makes it impossible to
fit weights in a double buffer in sram.
The worst compression ratio from compression, is used
to decide if weights can be fit in sram.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I9458769866b3f9fc15659185aae09658ed10fb38
|
|
Overflow could occur in the calculation of the LUT table for sigmoid,
for big negative inputs.
Change-Id: I62a33c68de03e9a7a7e4fe2cbd5835c384dc3643
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
Min and max operations was not passed through
the checking of elementwize OPs in the supported
operator checking.
Changed so they are passed through this check as well.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I358a121de33882802415d97d9ed5dbee53233f77
|
|
Fixed crash in networks with 5D tensors.
Fixed crash for (int32) tensors without quantization.
Added validity checks for concatenation.
Moved unfusing of activation function from tflite_reader to graph_optimiser.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: Ib9ba8891dc95ef5491e15d0feedef44331a26393
|
|
SHRAM is removed from performance reports, as the SHRAM numbers only
include LUT usage.
Change-Id: I5d92bb3be9c8e38dad26ac8ef97c84ecb0aff2fa
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
Fixed issue in removal of reshapes
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Id6081de8d6b7b6815cc5e56881c20e075214c407
|
|
Uses LUT for int8/uint8 based tanh/sigmoid.
Change-Id: Ib6ac5a5c958ab9a17e47f620b22c3e22d8d60321
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
Added check for inf numbers for all scales.
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
Change-Id: I84fcae429be4869d8489f66bef26863c254104cd
|
|
Updated supported operator checks for StridedSlice:
- allow negative indices in begin/end values
- added more checks on shapes
Change-Id: I3ac76bfa6b313f0e2250f0749f152fb0e3aa033c
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
If IFM/OFM is not 4d rescaling ops are added to ReLus with
different scaling.
Change-Id: I631d44fc8a51fb476b9f62ef90eda26eef3d35f3
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
|
|
Attempts to use fast storage for feature maps used in between
cascaded passes.
This is only relevant for system configurations where feature maps
are by default not placed in SRAM, but there is SRAM for fast storage.
Change-Id: I207b7cf32cfcb5bea3e6b93c2da1161c4af5221d
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
Change-Id: I750ec63a0e37b38feaf4cbdcc883fdbef92bccdf
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
|
|
Fixed issue with checking if axis corresponds to C-dim
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I72d9fd2c9fca642b5ab326324a63111b01c5de98
|
|
Assign different equivalence ids to weights with same values but
different compression, to ensure correct addressing.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I13aabad71520e4f4a78fb2d6a81740bdd4d1256c
|
|
- Added check for non-constant weights in supported operators
- Added check ifm & ifm2 shapes
- Handle None tensors for CPU operators
- Handle missing attributes for Cast operator
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
Change-Id: I2f16d3d44d0c6da5237550b39273cdb9cc3c7607
|
|
Fixed incorrect ofm shape for some of the intermediate mul
operations in softmax int8/uint8.
Change-Id: I82351c1eb6a66b93280752f4cc00e2d0744d33b2
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
|
|
Added support to convert batched FC to conv.
This enables choosing a suitable block-size.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Idc49e4fb6d29c554f10a38ece7996a7b7795ffad
|
|
- Use non local memory as the base sram usage for a subgraph
- Make avoid_for_spilling more generic for all mem configs
Change-Id: I99cd30fe6a8ba075d5a70dc2138aa0635afaadb3
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
|
|
Compiled the new TensorFlow 2.3 schema and added the new Operator
BatchMatMul to tflite_mapping.py.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: Ie62517bd56a6497820e4f1ef20326a4fd2ca89b0
|
|
Added logic for not using 40bit ACC for softmax int16.
Change-Id: I02b376040e19b48e8aaa65d48ffc7c47a0b9b187
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
|
|
Added a static class TensorAddressMap that stores all Tensor addresses
based on their equivalence_id. Made the "address" field into a property
which getter and setter looks up/sets the tensor's address in
TensorAddressMap.
This makes the references to cpu_tensor/npu_tensor obsolete and they
have been removed.
Addition to scheduler: avoid SRAM spilling if an op has consumers in
other subgraphs.
Minor rework in LUTState; it will now assign a unique equivalence_id to
the SHRAM lut tensor to avoid issues with addressing. The equivalent
checks in LUTState now compares the values of the LUT instead of the the
equivalence_id.
Updated LUT unit tests accordingly.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I41de5a8a4e5f07b77d6544d8d4034b754993e503
|
|
Allocate live ranges with longer life time first.
On average this gives better memory usage.
Change-Id: Id89e9e36a944169a2f10ce7f6e869397ef0abaf0
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
A Split operation with num_splits=1 is essentially
a NOP. This commit adds a graph optimisation function
which replaces said Split ops with an Identity op for
later pruning.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I0b0c535f214f54ee4c255662a18c37543bdc6d64
|
|
Improved unit test coverage of fp_math.py
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I883fd984a1bfa67102826a400380e41a363fc59d
|
|
- Only insert DMA op when IFM is for broadcasting and can't fit into
SHRAM
Change-Id: I3a7137bbc6311ce247353f04b7ab29e1bcbfe1f3
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
|
|
In the event we have a relu op with different input and output scales,
we need to fuse it with a nop avgpool.
Also refactor the existing avgpool nop code to a common function.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: Iedf4513e7595ee4ee1777ba0b1eb38a8df8aed5e
|
|
Addded functionality for removing reshape OPs,
that enclose an Elementwize OP with only one non-constant
Tensor.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Idaac50cfbd732e2667668be2baa059673236cc56
|
|
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
Change-Id: I49c8d283eaa8d44839b94aaf4e90ec35365dc13f
|
|
- Fixed SHRAM allocation for 8 and 16-bit elementwise ops
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I909a86d76e4ee6eab612aae827038b82703f28dc
|
|
We have a number of sets for grouping specific ops together but arent
used that much in code. This updates the file to better utilise these
sets.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: I719212671f8bdebc32576278f703549f0937ff65
|
|
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: I3c3ed73a6db39615ddf5987dc5696b6b09682be0
|
|
Allows fusing of LUT with a preceding operator regardless of
input/output scale.
Change-Id: Ia378adbb3fe61d71299feb085f7313377e0efa39
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
|
|
If a tflite file with no ops but just the input/output tensor is given,
vela wrote an empty optimised tflite file with no tensors given.
This fixes that by allowing all placeholder tensors to also be
serialised on write.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: If79817100869e712a75264889f401e38de0b1e7a
|
|
Added batching to softmax by reshaping the input.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I0b516f9bf2410fb86372b229beba4a7280c498cc
|
|
Removed CLI-option permanent-storage
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I03e03205a183bd538292a73a07b095546fa3d95a
|