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2020-10-21MLBEDSW-603: Improve cycle estimation in elementwise opsDiqing Zhong
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com> Change-Id: I9f3671041c2b1497519cf42b5f52e3cd01d9c10a (cherry picked from commit e8c989f5236cce12d07a6644329935dbbf0ee8e6)
2020-10-20MLBEDSW-3268: Refactor mark_tensorsLouis Verhaard
- Refactored mark_tensor_purpose - Initial weight compression is now always done in insert_dma - Removed mark_tensor_format Change-Id: Ic719b9bcd1d27e1390d7b9ce8cd21795139ec814 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-19MLBEDSW-3194: Updated elementwise IFM banks countAndreas Nevalainen
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: Ie404a0c13e7c7de0eff649f77e0147a0f3d73acd
2020-10-19MLBEDSW-2412 Refactor constraints for conv opsMichael McGeagh
Using a new system to report constraints, replaced existing functionality for checking conv-like ops. This new system will allow reporting of all constraints regardless of any input network. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: If81177deca2a3b57c9dd9a3a08868cbc9cef0c23
2020-10-16MLBEDSW-3004: UnpackReshaped can't be serialisedDwight Lidman
This commit fixes a bug where a rewritten Unpack operator is placed on the CPU and crashes Vela during serialisation due to the type having changed and there not being a mapping for the modified op type. The solution is to move the fixup_unpack_output function to the graph optimisation pass B, allowing the supported op check to run before it. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ic6bd4c70a478fd61adf377cb487f5b9253130314
2020-10-15MLBEDSW-3219: Suppress CPU info Const/PlaceholderLouis Verhaard
Suppress info print that Const/Placeholder/SubgraphInput are not supported on the NPU. Change-Id: I6f323b64185b01b619b584c1473ae61d010ab3a4 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-14Revert "MLBEDSW-3219: Suppress CPU info for Const/Placeholder"patrik.gustavsson
This reverts commit 04986c0016e59993563490fe67052371fc0e1ad2. Reason for revert: Merged by mistake Change-Id: I150ad9ba7074ad1e80f21180aeba56a454d9f748
2020-10-14MLBEDSW-3219: Suppress CPU info for Const/PlaceholderLouis Verhaard
Suppress info print that Const/Placeholder/SubgraphInput are not supported on the NPU. Change-Id: I689d25481df0cd10487484c9f639e4253df081ee Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-13vela: Improve extra info in constraint checksMichael McGeagh
Keeping the constraint functions consistent with each other Added specific tensor names in the extra info Added operator name to the warning generated This should help easily identify specific problematic nodes in a graph and give a good enough explanation as to why they are placed on the CPU Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Ie5bbdd31e5e75fe37e3d8bb8fee1d260080bce83
2020-10-13MLBEDSW-3219 Added info print for unsupported operatorPatrik Gustavsson
Added info print for unsupported operator Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I1002d1c2249661bff17ef86d9500d1aeb2a1e38e
2020-10-12MLBEDSW-3230 Remove restriction of batching 16 for FCPatrik Gustavsson
Vela supports batching of FC, restriction removed. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ica56738f1b2676628644fc44f2039a24807f5ccb
2020-10-12MLBEDSW-3220: missing "fused_activation_function" caused crashLouis Verhaard
Vela could crash in operator serialization if "fused_activation_function" was not set. Change-Id: I7f2364b0849fd371dee87e26c6d33d44ce8cec26 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-12MLBEDSW-3154 Bug fix for LUT ops with IFM from SplitSliceReadLouis Verhaard
- Incorrect length check in high level command stream generator - Improved tensor names related to LUT based operations Change-Id: Ib8844a35a986e2dbef095df23f143f4633b255f9 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-12MLBEDSW-3061: Update supported_operators.pyDwight Lidman
This commit changes and amends some parts of the restriction functions in order to make sure operators are correctly placed. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I336cf33a874c9078a5bbf81ce129ff917dbc5e9a
2020-10-09MLBEDSW-3218: Added operator indices Quantize/DequantizeLouis Verhaard
Change-Id: Idcf1665f95ddecc2a12ff0e714f645263981d501 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-09MLBEDSW-2985 Avoid reshape if input when there are no valuesPatrik Gustavsson
Added check so that inputs with no values are not reshaped. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Id5e53b093508583c2d70ba7e337869db3de32701
2020-10-08MLBEDSW-3148: Refactor OperationLouis Verhaard
- op.type is now an enum instead of a string - Removed unused operator codes - Refactored some attributes like npu_block_type, fused_activation_function - Refactored operator index calculation - Refactored a number of operator sets Change-Id: I641f65ee375794b7aec42abc0664251ae37d78e8 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-07MLBEDSW-3154 Fix issue for checking axis in concatPatrik Gustavsson
Fix issue for checking axis in concat, now allowing 0. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I85a5fc3dacdfc66dc01b0e05048dd100254fddff
2020-10-07Updated pre-commit config to use 19.10b0 version of BlackDwight Lidman
The latest "stable" version of Black formats code differently from the 19.10b0 version that has been used in the past, which introduces unwelcome formatting changes in newer commits. This commit explicitly sets the revision to 19.10b0. It also changes the repo parameter to point to the new URL. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I20c73f0c87434143f62282f5f0399f73cedfd6ce
2020-10-06Vela: Fix issue with elementwise block config validationTim Hall
- Presence of accumulators in validation was preventing some elementwise configurations from being chosen. This commit sets accumulator requirement to zero before validating the shared buffer config. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Id79f80afb12f77274ade53f7678c3b2e56aef059
2020-10-05MLBEDSW-2412 Replace generic restrictionsMichael McGeagh
A new mechanism to report generic restrictions/constraints for operators has been implemented. Each check is its own defined function, and has a general reason for the constraint defined as its docstring. This allows us to query all reasons up front and report this without having to run through real data to trigger the checks. This is part of a larger refactoring and the specific restrictions will be replaced by a similar mechanism. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Id3fb2639f91cfac5fc5b8c14f7620de1a85972b2
2020-10-05vela: SupportedOperators promote to class instanceMichael McGeagh
Part of larger refactoring. The sets of operators do not need to be instance attributes and are not expected to be modified at runtime. This in turn allows almost all functions to become class methods. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I7dc24d65cdd6c4bda641b3d6133b3134302a552f
2020-10-02MLBEDSW-3062 Updated SECURITY.mdPatrik Gustavsson
Issues should be reported via arm-security@arm.com Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Iea06e77dbabedcbe334dd63f644b63ec737f82df
2020-10-02MLBEDSW-3060 Adjust check if weights fit in sramPatrik Gustavsson
When deciding if weights fit sram: A compression of the weights has been added when a weight compression test limit makes it impossible to fit weights in a double buffer in sram. The worst compression ratio from compression, is used to decide if weights can be fit in sram. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I9458769866b3f9fc15659185aae09658ed10fb38
2020-09-30MLBEDSW-3153: Fix overflow in sigmoid LUTLouis Verhaard
Overflow could occur in the calculation of the LUT table for sigmoid, for big negative inputs. Change-Id: I62a33c68de03e9a7a7e4fe2cbd5835c384dc3643 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-30MLBEDSW-3001 Fix Min Max OPs not properly checkedPatrik Gustavsson
Min and max operations was not passed through the checking of elementwize OPs in the supported operator checking. Changed so they are passed through this check as well. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I358a121de33882802415d97d9ed5dbee53233f77
2020-09-30[MLBEDSW-2802] Fix 5D tensor crashFredrik Svedberg
Fixed crash in networks with 5D tensors. Fixed crash for (int32) tensors without quantization. Added validity checks for concatenation. Moved unfusing of activation function from tflite_reader to graph_optimiser. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: Ib9ba8891dc95ef5491e15d0feedef44331a26393
2020-09-30MLBEDSW-3025: Remove SHRAM from reportsLouis Verhaard
SHRAM is removed from performance reports, as the SHRAM numbers only include LUT usage. Change-Id: I5d92bb3be9c8e38dad26ac8ef97c84ecb0aff2fa Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-29MLBEDSW-3032 Fixed issue in removal of reshapesPatrik Gustavsson
Fixed issue in removal of reshapes Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Id6081de8d6b7b6815cc5e56881c20e075214c407
2020-09-29MLBEDSW-2031: LUT support tanh/sigmoidLouis Verhaard
Uses LUT for int8/uint8 based tanh/sigmoid. Change-Id: Ib6ac5a5c958ab9a17e47f620b22c3e22d8d60321 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-28MLBEDSW-2885: Fix overflow from inf numberAndreas Nevalainen
Added check for inf numbers for all scales. Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: I84fcae429be4869d8489f66bef26863c254104cd
2020-09-28MLBEDSW-3035: Updated StridedSlice checksLouis Verhaard
Updated supported operator checks for StridedSlice: - allow negative indices in begin/end values - added more checks on shapes Change-Id: I3ac76bfa6b313f0e2250f0749f152fb0e3aa033c Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-25MLBEDSW-2811: Add rescaling to ReLus with different scalingAndreas Nevalainen
If IFM/OFM is not 4d rescaling ops are added to ReLus with different scaling. Change-Id: I631d44fc8a51fb476b9f62ef90eda26eef3d35f3 Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
2020-09-25MLBEDSW-2337: Intermediate feature maps in fast storageLouis Verhaard
Attempts to use fast storage for feature maps used in between cascaded passes. This is only relevant for system configurations where feature maps are by default not placed in SRAM, but there is SRAM for fast storage. Change-Id: I207b7cf32cfcb5bea3e6b93c2da1161c4af5221d Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-24MLBEDSW-2788 Fix crash on non-constant weight tensorsAndreas Nevalainen
Change-Id: I750ec63a0e37b38feaf4cbdcc883fdbef92bccdf Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
2020-09-23MLBEDSW-3018 Change to check for avoiding NHCWB16Patrik Gustavsson
Fixed issue with checking if axis corresponds to C-dim Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I72d9fd2c9fca642b5ab326324a63111b01c5de98
2020-09-23MLBEDSW-3070: Fix addressing of weightsLouis Verhaard
Assign different equivalence ids to weights with same values but different compression, to ensure correct addressing. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I13aabad71520e4f4a78fb2d6a81740bdd4d1256c
2020-09-22MLBEDSW-2813: Handle non-const weights and check shapesAndreas Nevalainen
- Added check for non-constant weights in supported operators - Added check ifm & ifm2 shapes - Handle None tensors for CPU operators - Handle missing attributes for Cast operator Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: I2f16d3d44d0c6da5237550b39273cdb9cc3c7607
2020-09-21Fix int8/uint8 softmax mul shapeFredrik Svedberg
Fixed incorrect ofm shape for some of the intermediate mul operations in softmax int8/uint8. Change-Id: I82351c1eb6a66b93280752f4cc00e2d0744d33b2 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-09-21MLBEDSW-1693 Convert batched FC to ConvPatrik Gustavsson
Added support to convert batched FC to conv. This enables choosing a suitable block-size. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Idc49e4fb6d29c554f10a38ece7996a7b7795ffad
2020-09-21MLBEDSW-2816: Fix assert in schedulerDiqing Zhong
- Use non local memory as the base sram usage for a subgraph - Make avoid_for_spilling more generic for all mem configs Change-Id: I99cd30fe6a8ba075d5a70dc2138aa0635afaadb3 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2020-09-18MLBEDSW-2734: TensorFlow 2.3 compatibilityJacob Bohlin
Compiled the new TensorFlow 2.3 schema and added the new Operator BatchMatMul to tflite_mapping.py. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: Ie62517bd56a6497820e4f1ef20326a4fd2ca89b0
2020-09-17[MLBEDSW-2638] Do not use 40bit ACC for softmax int16Fredrik Svedberg
Added logic for not using 40bit ACC for softmax int16. Change-Id: I02b376040e19b48e8aaa65d48ffc7c47a0b9b187 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-09-17MLBEDSW-2809: Redo the Tensor addressingJacob Bohlin
Added a static class TensorAddressMap that stores all Tensor addresses based on their equivalence_id. Made the "address" field into a property which getter and setter looks up/sets the tensor's address in TensorAddressMap. This makes the references to cpu_tensor/npu_tensor obsolete and they have been removed. Addition to scheduler: avoid SRAM spilling if an op has consumers in other subgraphs. Minor rework in LUTState; it will now assign a unique equivalence_id to the SHRAM lut tensor to avoid issues with addressing. The equivalent checks in LUTState now compares the values of the LUT instead of the the equivalence_id. Updated LUT unit tests accordingly. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I41de5a8a4e5f07b77d6544d8d4034b754993e503
2020-09-17MLBEDSW-2377: Greedy allocator improvementLouis Verhaard
Allocate live ranges with longer life time first. On average this gives better memory usage. Change-Id: Id89e9e36a944169a2f10ce7f6e869397ef0abaf0 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-17MLBEDSW-3008: Replace Split ops with IdentityDwight Lidman
A Split operation with num_splits=1 is essentially a NOP. This commit adds a graph optimisation function which replaces said Split ops with an Identity op for later pruning. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I0b0c535f214f54ee4c255662a18c37543bdc6d64
2020-09-14[MLBEDSW-2845] Improve unit test coverage of fp_mathFredrik Svedberg
Improved unit test coverage of fp_math.py Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I883fd984a1bfa67102826a400380e41a363fc59d
2020-09-14MLBEDSW-2816: remove constant array from SRAMDiqing Zhong
- Only insert DMA op when IFM is for broadcasting and can't fit into SHRAM Change-Id: I3a7137bbc6311ce247353f04b7ab29e1bcbfe1f3 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2020-09-11MLBEDSW-2745 Support relus with differing scalesMichael McGeagh
In the event we have a relu op with different input and output scales, we need to fuse it with a nop avgpool. Also refactor the existing avgpool nop code to a common function. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Iedf4513e7595ee4ee1777ba0b1eb38a8df8aed5e
2020-09-11MLBEDSW-2994 Remove undesired reshape OPsPatrik Gustavsson
Addded functionality for removing reshape OPs, that enclose an Elementwize OP with only one non-constant Tensor. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Idaac50cfbd732e2667668be2baa059673236cc56
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