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2020-09-21MLBEDSW-2816: Fix assert in schedulerDiqing Zhong
- Use non local memory as the base sram usage for a subgraph - Make avoid_for_spilling more generic for all mem configs Change-Id: I99cd30fe6a8ba075d5a70dc2138aa0635afaadb3 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2020-09-18MLBEDSW-2734: TensorFlow 2.3 compatibilityJacob Bohlin
Compiled the new TensorFlow 2.3 schema and added the new Operator BatchMatMul to tflite_mapping.py. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: Ie62517bd56a6497820e4f1ef20326a4fd2ca89b0
2020-09-17[MLBEDSW-2638] Do not use 40bit ACC for softmax int16Fredrik Svedberg
Added logic for not using 40bit ACC for softmax int16. Change-Id: I02b376040e19b48e8aaa65d48ffc7c47a0b9b187 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-09-17MLBEDSW-2809: Redo the Tensor addressingJacob Bohlin
Added a static class TensorAddressMap that stores all Tensor addresses based on their equivalence_id. Made the "address" field into a property which getter and setter looks up/sets the tensor's address in TensorAddressMap. This makes the references to cpu_tensor/npu_tensor obsolete and they have been removed. Addition to scheduler: avoid SRAM spilling if an op has consumers in other subgraphs. Minor rework in LUTState; it will now assign a unique equivalence_id to the SHRAM lut tensor to avoid issues with addressing. The equivalent checks in LUTState now compares the values of the LUT instead of the the equivalence_id. Updated LUT unit tests accordingly. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I41de5a8a4e5f07b77d6544d8d4034b754993e503
2020-09-17MLBEDSW-2377: Greedy allocator improvementLouis Verhaard
Allocate live ranges with longer life time first. On average this gives better memory usage. Change-Id: Id89e9e36a944169a2f10ce7f6e869397ef0abaf0 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-17MLBEDSW-3008: Replace Split ops with IdentityDwight Lidman
A Split operation with num_splits=1 is essentially a NOP. This commit adds a graph optimisation function which replaces said Split ops with an Identity op for later pruning. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I0b0c535f214f54ee4c255662a18c37543bdc6d64
2020-09-14[MLBEDSW-2845] Improve unit test coverage of fp_mathFredrik Svedberg
Improved unit test coverage of fp_math.py Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I883fd984a1bfa67102826a400380e41a363fc59d
2020-09-14MLBEDSW-2816: remove constant array from SRAMDiqing Zhong
- Only insert DMA op when IFM is for broadcasting and can't fit into SHRAM Change-Id: I3a7137bbc6311ce247353f04b7ab29e1bcbfe1f3 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2020-09-11MLBEDSW-2745 Support relus with differing scalesMichael McGeagh
In the event we have a relu op with different input and output scales, we need to fuse it with a nop avgpool. Also refactor the existing avgpool nop code to a common function. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Iedf4513e7595ee4ee1777ba0b1eb38a8df8aed5e
2020-09-11MLBEDSW-2994 Remove undesired reshape OPsPatrik Gustavsson
Addded functionality for removing reshape OPs, that enclose an Elementwize OP with only one non-constant Tensor. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Idaac50cfbd732e2667668be2baa059673236cc56
2020-09-11MLBEDSW-2813: Handle None tensor when parsing operatorsAndreas Nevalainen
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: I49c8d283eaa8d44839b94aaf4e90ec35365dc13f
2020-09-09vela: SHRAM alloc too big for some elementwise opsTim Hall
- Fixed SHRAM allocation for 8 and 16-bit elementwise ops Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I909a86d76e4ee6eab612aae827038b82703f28dc
2020-09-08vela: Refactor op sets in graph_optimiserMichael McGeagh
We have a number of sets for grouping specific ops together but arent used that much in code. This updates the file to better utilise these sets. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I719212671f8bdebc32576278f703549f0937ff65
2020-09-08optim: Fix issue with IFM streaming of LUTMichael McGeagh
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I3c3ed73a6db39615ddf5987dc5696b6b09682be0
2020-09-08MLBEDSW-2935: LUT fusing with preceding operatorLouis Verhaard
Allows fusing of LUT with a preceding operator regardless of input/output scale. Change-Id: Ia378adbb3fe61d71299feb085f7313377e0efa39 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-07MLBEDSW-2874 Fix writing out empty tflite filesMichael McGeagh
If a tflite file with no ops but just the input/output tensor is given, vela wrote an empty optimised tflite file with no tensors given. This fixes that by allowing all placeholder tensors to also be serialised on write. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: If79817100869e712a75264889f401e38de0b1e7a
2020-09-07[MLBEDSW-2928] Add batching to softmaxFredrik Svedberg
Added batching to softmax by reshaping the input. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I0b516f9bf2410fb86372b229beba4a7280c498cc
2020-09-04MLBEDSW-2819 Removed CLI-option permanent-storagePatrik Gustavsson
Removed CLI-option permanent-storage Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I03e03205a183bd538292a73a07b095546fa3d95a
2020-09-03MLBEDSW-2814 Add support for inferred size in SplitVPatrik Gustavsson
For SplitV sizesplit can contain one -1 indicating that dimension is to be inferred. Support added to handle this. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ib9fc8dd2ee1749e81a978d85f2d4a016698bb441
2020-09-03MLBEDSW-2567: CLI option to specify allocation alignmentJacob Bohlin
Added the CLI option. Only applies to CPU tensors. Added an AllocationError which is raised when Allocation fails. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I89164dea3ac7b7add7bc40aec2ce8fe50600105d
2020-09-03[MLBEDSW-2905] Fix int16 multiplier saturationFredrik Svedberg
Fix int16 multiplier saturation to match the reference. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I4a9c859482f7deb3899f90c7e9eb40c255ee4c45
2020-09-03MLBEDSW-2906: Only add padding fields to Npu opsJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I75aad9bf59ad76ee6a0c0feb4d7299b50d787fe8
2020-09-01MLBEDSW-2903 Split mapping to tensor1.2.0.rc31.2.0Patrik Gustavsson
Split mapping to tensor Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ic143f3b4d37f6904edd8f119eff1d108f70b5026
2020-08-31MLBEDSW-2804: Removed invalid assert for shift rangeJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I857aeb7aeb34f4b8ea47e6ac954cead268335e32
2020-08-31MLBEDSW-2915: Added None check for bias before checking restrictionsJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I04618fd0d29075e7d3f8f27a320129603f045163
2020-08-30MLBEDSW-2919: bringup: int16 avgpool diff on FPGATim Hall
- Set ACC_FORAMT to 32-bit for pooling operations. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I69ebd08c2db4c5ec966ca13c872c9b0c8330bb6f
2020-08-29MLBEDSW-2804: Bias data type check wrongTim Hall
- Fixed bias check to use quantised values. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I6d87439938b9b5aeec87814e5a30d59fd06d5748
2020-08-28MLBEDSW-2900: softmax output diff on FPGATim Hall
- Corrected the rounding mode for softmax Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: If136491c7668e85fba1e2c56c8cff11aa32db328
2020-08-28[MLBEDSW-2900] zero point fix for int32 ifmFredrik Svedberg
Fixed a zero point issue for int32 ifm. Change-Id: I9149cb24d5b030ea5216a028a113518e458a8d15 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-08-28MLBEDSW-2688: LUT calculation with different in/out scaleLouis Verhaard
Enables LUT for LeakyRelu with int8/uint8 even if input scale is different from the output scale. Fusing LUT with a previous operator for this situation requires further work. Change-Id: I9eddfe36f457e763d44eb3e05fbe240eac7cfec9 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-08-28MLBEDSW-2411: Update README with example networksTim Hall
- Added reference to TensorFlow Hub - Updated relative .md links to release location Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I7f7b3508bd530d76681d25594ea7ff8241fe964d
2020-08-28MLBEDSW-2889: NHCWB16 format issue at end of subgraphTim Hall
- Processing reshapes at the end of NPU subgraphs selected NHCWB16 tensor format before handing over to the CPU. This commit detects end-of-subgraph during the reshape-consumers compatibility check and chooses NHWC format instead. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ieefdbecdba1a6183d79d3ac4d2505503dbf321cb
2020-08-28MLBEDSW-2804: Added bias data type checkJacob Bohlin
Allows int64 data type to be used as long as all values can be packed into a int40 value. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I0e25ec482e3ea765a5fd00bcf7e212a9e65a1461
2020-08-28MLBEDSW-2839 Update release notes for 1.2.0Michael McGeagh
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I3aa686bd0ece68af5840bcabbdb5702ba047d3de
2020-08-27[MLBEDSW-2857] Fix serialisation of non byte tensorsFredrik Svedberg
Fixed serialisation of scalar ifm tensors with values larger than byte sized. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I2714398db91b83f24e5271c1d5de1c0e8211f9ab
2020-08-27[MLBEDSW-2846] Do not use NHCWB16 for reduce_sum int32Fredrik Svedberg
Added checks for not using NHCWB16 for reduce_sum int32 which makes int8/uint8 softmax work. Also enabled softmax graph rewrite by default and fixed a saturation problem. Change-Id: Ic01bd9ece7e5c3edb2900b7915cc747efe9e5760 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-08-27Small fix for Softmax regressionJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I287c24725126c169afec779b921e43c3ab26f739
2020-08-27MLBEDSW-2786: Fix IFM order in binary operationDiqing Zhong
- Setup ifm/ifm2 based on primary op's inputs Change-Id: I727eab473165d7cc876b70fa8873fbc0c1480fb5 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2020-08-27MLBEDSW-2719: Update kernel size checkAndreas Nevalainen
Updated kernel size check, width and height was swapped and added weight sum check. Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: Idb18cf258ac19b3a0d71134dab5a117bcd778b59
2020-08-26MLBEDSW-2686: Use NPU tensor format for noop reshapes.1.2.0.rc2Tim Hall
- Reshapes that merely add/remove dimensions, rather than re-layout the data need not fall back to NHWC. This commit allows reshapes betweeen NPU operators to use NHCWB16. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ieb7745e586bf324e92e741a04b74caf7285f4b8b
2020-08-26Update to HI 1.0.6Stefan Nannesson
Signed-off-by: Stefan Nannesson <stefan.nannesson@arm.com> Change-Id: I7ad0b8e5b2431b46b53f51d809ca2642039a0012
2020-08-26MLBEDSW-2688: use LeakyRelu for int16Louis Verhaard
For int16, using LeakyRelu (with bug fix) gives exactly the same results as Mul+Max if input/output scales are the same. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I4f4db464d77b0aaf0d25ddfca534f91d08db548d
2020-08-26MLBED-2822 Added CLI-opt for weight size est.Patrik Gustavsson
Added --weight-estimation-scaling, which enables additional scaling of weight compression scale estimate. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Idcda41257f44901d3a3f345341e07fb1ae8585a9
2020-08-26MLBEDSW-2847: Fix for TransposeConv crash and u8 output diffJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I2cb3f6639e4bb8a984fa3647ee7b4678ed6f5890
2020-08-26MLBEDSW-2688: LUT DMA may require kernel waitLouis Verhaard
LUT related updates specific for 16K SHRAM: - prevent LUT DMA transfer from overwriting accumulator SHRAM of an ongoing operation - do not use the last 2K of SHRAM as accumulator during LUT operations Change-Id: I17066e0410c6f07b125ed245002d7b19269a7a8a Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-08-25MLBEDSW-2867: Split operators get placed on CPUDwight Lidman
This commit fixes a bug wherein Split operators are being erroneously placed on the CPU due to a 0-dimensional input that disqualifies it from NPU placement; a restriction introduced in a recent commit. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I83c047ddf071d662343087c69bdb2a014dd209c3
2020-08-24MLBEDSW-2654: Convert Resizebilinear to a number of 2x2 poolsCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: Ida307afc33cd7963bdeb505df400732a3efcc846
2020-08-24MLBEDSW-2688: LeakyRelu rewrite to LUT or MUL/MAXLouis Verhaard
Replaces LeakyRelu operations with LUT activation function when possible, else to a combination of multiplication/maximization. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I3d2eb2dba7145997c3cc711d0ef18ab355fbb416
2020-08-21MLBEDSW-2646: Refactor unknown operator serialisation1.2.0.rc1Tim Hall
- Minor cleanup of register command stream generator too Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I0514622402ee9b0557769dd7c7decfddecc87ffa
2020-08-21MLBEDSW-2679: Tensor quant comparison is incorrectTim Hall
- Fixed bug with the supported operator check rejecting operators based upon an incorrect comparison of the tensor quantisations Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ibd0eb50077465d2c515c6ee10394d9b43cdf730c
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