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author | Tim Hall <tim.hall@arm.com> | 2022-05-04 16:20:43 +0100 |
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committer | Tim Hall <tim.hall@arm.com> | 2022-05-04 16:26:09 +0100 |
commit | b5df773e92051004158046b0ed2c7b802198de6e (patch) | |
tree | 7d738a28a63b66a20f379acbdfc6c3e7c4a98a61 /ethosu/vela/high_level_command_to_npu_op.py | |
parent | 95b07c1c0fed6a985607131e59a593786d40b389 (diff) | |
download | ethos-u-vela-b5df773e92051004158046b0ed2c7b802198de6e.tar.gz |
Revert "MLBEDSW-6263: Use separate tensors for double buffering"
This reverts commit cc5f4de1c35ba44fca7ff6295c6ae846f8242344.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I0fa5babfe9ad9ec668720d04fe1c16d9a9092131
Diffstat (limited to 'ethosu/vela/high_level_command_to_npu_op.py')
-rw-r--r-- | ethosu/vela/high_level_command_to_npu_op.py | 38 |
1 files changed, 23 insertions, 15 deletions
diff --git a/ethosu/vela/high_level_command_to_npu_op.py b/ethosu/vela/high_level_command_to_npu_op.py index e6bfc1c4..3a78d6fb 100644 --- a/ethosu/vela/high_level_command_to_npu_op.py +++ b/ethosu/vela/high_level_command_to_npu_op.py @@ -68,6 +68,7 @@ from .tensor import MemType from .tensor import Tensor from .tensor import TensorFormat from .tensor import TensorPurpose +from .tensor import TensorSubPurpose from .weight_compressor import NpuWeightTensor from .weight_compressor import WeightKey @@ -201,15 +202,9 @@ def get_mem_limits_for_regions(arch: ArchitectureFeatures) -> Dict[int, int]: return mem_limits -def get_upscale(op: Operation) -> NpuResamplingMode: - upscale = NpuResamplingMode.NONE - if op.type == Op.ResizeBilinear: - # perform nearest neighbor upscale - upscale = NpuResamplingMode.NEAREST - elif op.type == Op.Conv2DBackpropInputSwitchedBias: - # perform insert zero upscale - upscale = NpuResamplingMode.TRANSPOSE - return upscale +def get_double_buffer_offset(arch: ArchitectureFeatures, range_index: int, core: int) -> int: + """Returns 0 if the first half of a double buffer should be used, 1 if the second half should be used""" + return ((range_index - core) // arch.ncores) % 2 def get_ifm_depth(npu_block_type: NpuBlockType, ifm_box: Box, ofm_box: Box) -> int: @@ -319,13 +314,20 @@ def create_weights( key = WeightKey(core, weight_box.start_coord[-1]) if key in w_tensor_src.encoded_ranges: weight_range = w_tensor_src.encoded_ranges[key] - if weight_tensor == w_tensor_src: - # Straight from source tensor - address = weight_tensor.address + weight_range.offset - else: - # Weight buffered tensor + if weight_tensor.sub_purpose == TensorSubPurpose.DoubleBuffer: + assert weight_tensor != w_tensor_src + # Double buffered inside weight_tensor address = weight_tensor.address + core_offset + address += get_double_buffer_offset(arch, weight_range.index, core) * w_tensor_src.max_range_bytes core_offset += round_up(weight_range.total_bytes, 16) + else: + if weight_tensor == w_tensor_src: + # Straight from source tensor + address = weight_tensor.address + weight_range.offset + else: + # Single buffered inside weight tensor + address = weight_tensor.address + core_offset + core_offset += round_up(weight_range.total_bytes, 16) # Location of weights in tensor addr_range = NpuAddressRange( @@ -524,7 +526,13 @@ def create_dma_op(cmd: DMA, arch: ArchitectureFeatures) -> NpuDmaOperation: if core == 0: weight_range = cmd.in_tensor.encoded_ranges[key] src_addr = cmd.in_tensor.address + weight_range.offset - dest_addr = cmd.out_tensor.address + + if cmd.out_tensor.sub_purpose == TensorSubPurpose.DoubleBuffer: + dest_addr = cmd.out_tensor.address + cmd.in_tensor.max_range_bytes * ( + get_double_buffer_offset(arch, weight_range.index, core) + ) + else: + dest_addr = cmd.out_tensor.address else: start_coord = cmd.box.start_coord src_addr = cmd.in_tensor.address_for_coordinate(start_coord) |