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| author | Diqing Zhong <diqing.zhong@arm.com> | 2020-10-02 13:18:42 +0200 |
|---|---|---|
| committer | tim.hall <tim.hall@arm.com> | 2020-11-11 11:14:53 +0000 |
| commit | 42e833d64918b666e81f957c56919d01bb6212cd (patch) | |
| tree | 7aab6627226a996e8b9bc89654f7b93b2670fbb2 /ethosu/vela/ethos_u55_regs | |
| parent | 09387e207aa736c464cf95c8a57609aa21b65d44 (diff) | |
| download | ethos-u-vela-42e833d64918b666e81f957c56919d01bb6212cd.tar.gz | |
MLBEDSW-3146: memory transfers cycle estimation
- DMA ops cycle estimation for the first pass
- fix a bug in ifm_blk_depth calculation
- fix a bug in sram bandwidth calculation
- merge dpu and elementwise cycles into npu cycles
- use str.format() in performance print
Change-Id: I78895416f47fc3c652743c5da13fc45630322371
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
(cherry picked from commit 5245e97a62c2fe54250f99b06e778f3e0c6dc376)
(cherry picked from commit 16e415677403fc04a90b1a7ec554761d38315640)
Diffstat (limited to 'ethosu/vela/ethos_u55_regs')
0 files changed, 0 insertions, 0 deletions