MLBEDSW-3685 Fix dangerous default value usage

Pylint W0102:
When a mutable value as list or dictionary is detected in a
default value for an argument.

Replace detected instances with None, and upon checking for None, sets
the default accordingly

Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: I4eb73d07d01d4cdefa586eb71b9c76746eee3b11

7 files changed, 60 insertions, 52 deletions

diff --git a/ethosu/vela/live_range.py b/ethosu/vela/live_range.py
index dbc0ce40..14e83a33 100644
--- a/ethosu/vela/live_range.py
+++ b/ethosu/vela/live_range.py
@@ -194,10 +194,7 @@ def merge_elementwise_op_ranges(ps, lr_graph, target_mem_area, target_mem_type_s
 
 
 def extract_live_ranges_from_passes(
-    sg,
-    target_mem_area,
-    target_mem_type_set=set((MemType.Scratch, MemType.Scratch_fast)),
-    ignore_subgraph_input_output_tensors=False,
+    sg, target_mem_area, target_mem_type_set=None, ignore_subgraph_input_output_tensors=False,
 ):
     lr_graph = LiveRangeGraph()
 
@@ -205,6 +202,9 @@ def extract_live_ranges_from_passes(
         lr_graph.ignore_tensors.update(sg.input_tensors)
         lr_graph.ignore_tensors.update(sg.output_tensors)
 
+    if target_mem_type_set is None:
+        target_mem_type_set = set((MemType.Scratch, MemType.Scratch_fast))
+
     # Try to merge live ranges of operations in the NPU subgraphs
     if sg.placement == PassPlacement.Npu:
         merge_op_ranges(sg, lr_graph, target_mem_area, target_mem_type_set)
diff --git a/ethosu/vela/model_reader.py b/ethosu/vela/model_reader.py
index 0f79f9b2..bb49b64a 100644
--- a/ethosu/vela/model_reader.py
+++ b/ethosu/vela/model_reader.py
@@ -29,8 +29,14 @@ class ModelReaderOptions:
     __repr__ = __str__
 
 
-def read_model(fname, options, feed_dict={}, output_node_names=[], initialisation_nodes=[]):
+def read_model(fname, options, feed_dict=None, output_node_names=None, initialisation_nodes=None):
     if fname.endswith(".tflite"):
+        if feed_dict is None:
+            feed_dict = {}
+        if output_node_names is None:
+            output_node_names = []
+        if initialisation_nodes is None:
+            initialisation_nodes = []
         return tflite_reader.read_tflite(
             fname,
             options.batch_size,
diff --git a/ethosu/vela/npu_performance.py b/ethosu/vela/npu_performance.py
index 9a6e8cd2..d28df97d 100644
--- a/ethosu/vela/npu_performance.py
+++ b/ethosu/vela/npu_performance.py
@@ -489,7 +489,7 @@ def estimate_memory_bandwidth(arch, mem_area, direction, tensor, block_size: Blo
     return bw * (max_burst_len / burst_len)
 
 
-def performance_metrics_for_pass(arch, ps, block_config=None, rewrite_list=[], force_outputs_to_fast_storage=False):
+def performance_metrics_for_pass(arch, ps, block_config=None, rewrite_list=None, force_outputs_to_fast_storage=False):
     if block_config is None:
         block_config = ps.block_config
     bws = make_bandwidth_array()
@@ -723,26 +723,27 @@ def performance_metrics_for_pass(arch, ps, block_config=None, rewrite_list=[], f
                 for tens in dma_op.inputs:
                     cycles[PassCycles.Npu] += tens.storage_size() / arch.memory_bandwidths_per_cycle[mem_area]
 
-    # apply the desired rewrites
-    for rewrite_op, tens, _, _, _, ps_to_rewrite in rewrite_list:
-        if ps != ps_to_rewrite:
-            continue
-        if rewrite_op == SchedulerRewrite.Nop:
-            pass  # these are fine, no bandwidth changes
-        elif rewrite_op in (SchedulerRewrite.ChangeTensorSubPurpose,):
-            if tens.purpose == TensorPurpose.FeatureMap:
-                bw = estimate_memory_bandwidth(
-                    arch,
-                    arch.fast_storage_mem_area,
-                    BandwidthDirection.Read,
-                    tens,
-                    ifm_block,
-                    replacement_read_bws[tens],
-                )
-            else:
-                bw = replacement_read_bws[tens]
-            bws[arch.fast_storage_mem_area][tens.purpose][BandwidthDirection.Read] += bw
-            replacement_read_bws[tens] = 0
+    if rewrite_list is not None:
+        # apply the desired rewrites
+        for rewrite_op, tens, _, _, _, ps_to_rewrite in rewrite_list:
+            if ps != ps_to_rewrite:
+                continue
+            if rewrite_op == SchedulerRewrite.Nop:
+                pass  # these are fine, no bandwidth changes
+            elif rewrite_op in (SchedulerRewrite.ChangeTensorSubPurpose,):
+                if tens.purpose == TensorPurpose.FeatureMap:
+                    bw = estimate_memory_bandwidth(
+                        arch,
+                        arch.fast_storage_mem_area,
+                        BandwidthDirection.Read,
+                        tens,
+                        ifm_block,
+                        replacement_read_bws[tens],
+                    )
+                else:
+                    bw = replacement_read_bws[tens]
+                bws[arch.fast_storage_mem_area][tens.purpose][BandwidthDirection.Read] += bw
+                replacement_read_bws[tens] = 0
 
     for tens in ps.outputs:
         if force_outputs_to_fast_storage:
diff --git a/ethosu/vela/stats_writer.py b/ethosu/vela/stats_writer.py
index e4b81561..494b25e7 100644
--- a/ethosu/vela/stats_writer.py
+++ b/ethosu/vela/stats_writer.py
@@ -236,7 +236,7 @@ def print_performance_metrics_for_strat(
     num_passes,
     num_cascaded_passes,
     n_operations=0,
-    cpu_operations=[],
+    cpu_operations=None,
     bits_per_element=None,
     show_cpu_operations=False,
     f=sys.stdout,
@@ -284,6 +284,9 @@ def print_performance_metrics_for_strat(
     print(file=f)
     print("{:d} passes fused into {:d}".format(num_passes, num_cascaded_passes), file=f)
 
+    if cpu_operations is None:
+        cpu_operations = []
+
     n_cpu_operations = len(cpu_operations)
     if n_operations > 0:
         print(
diff --git a/ethosu/vela/test/testutil.py b/ethosu/vela/test/testutil.py
index 4b2938b9..9ba39bc5 100644
--- a/ethosu/vela/test/testutil.py
+++ b/ethosu/vela/test/testutil.py
@@ -107,11 +107,12 @@ def create_op_with_quant_tensors(
     return op
 
 
-def create_op(op_type, inputs, output, attrs=dict()):
+def create_op(op_type, inputs, output, attrs=None):
     op = Operation(op_type, output.name + "_op")
     op.inputs = inputs
     op.outputs = [output]
-    op.attrs = attrs
+    if attrs is not None:
+        op.attrs = attrs
     return op
 
 
diff --git a/ethosu/vela/tflite_mapping.py b/ethosu/vela/tflite_mapping.py
index 20521e41..fe582614 100644
--- a/ethosu/vela/tflite_mapping.py
+++ b/ethosu/vela/tflite_mapping.py
@@ -333,28 +333,29 @@ def write_int_vector(builder, v):
 
 
 class OptionsSerializer:
-    def __init__(self, name, members=[]):
+    def __init__(self, name, members=None):
         self.name = name
         self.module = globals()[self.name]
         self.cls = getattr(self.module, self.name)
         self.builtin_opt_type = builtin_options_inv_map[self.cls]
         self.members = []
-        for mem in members:
-            deserialize = identity
-            serialize = identity_serialize
-            is_vector = False
-            if isinstance(mem, tuple):
-                if len(mem) == 3:
-                    mem, deserialize, serialize = mem
-                elif len(mem) == 2:
-                    mem, is_vector = mem
-                    deserialize = tuple
-                    serialize = write_int_vector
-                else:
-                    assert 0
-            underscore_mem = mem
-            camelcase_mem = underscore_to_camel_case(mem)
-            self.members.append((underscore_mem, camelcase_mem, deserialize, serialize, is_vector))
+        if members is not None:
+            for mem in members:
+                deserialize = identity
+                serialize = identity_serialize
+                is_vector = False
+                if isinstance(mem, tuple):
+                    if len(mem) == 3:
+                        mem, deserialize, serialize = mem
+                    elif len(mem) == 2:
+                        mem, is_vector = mem
+                        deserialize = tuple
+                        serialize = write_int_vector
+                    else:
+                        assert 0
+                underscore_mem = mem
+                camelcase_mem = underscore_to_camel_case(mem)
+                self.members.append((underscore_mem, camelcase_mem, deserialize, serialize, is_vector))
 
     def deserialize(self, op_data):
         builtin_options = op_data.BuiltinOptions()
diff --git a/ethosu/vela/tflite_reader.py b/ethosu/vela/tflite_reader.py
index 9e202154..93b97f6d 100644
--- a/ethosu/vela/tflite_reader.py
+++ b/ethosu/vela/tflite_reader.py
@@ -214,9 +214,7 @@ class TFLiteSubgraph:
 
 
 class TFLiteGraph:
-    def __init__(
-        self, filename, batch_size=1, feed_dict={}, output_node_names=[], initialisation_nodes=[],
-    ):
+    def __init__(self, filename, batch_size, feed_dict, output_node_names, initialisation_nodes):
 
         self.op_times = {}
         if batch_size is None:
@@ -275,9 +273,7 @@ class TFLiteGraph:
         return op_type, ser, custom_code
 
 
-def read_tflite(
-    filename, batch_size=1, feed_dict={}, output_node_names=[], initialisation_nodes=[],
-):
+def read_tflite(filename, batch_size, feed_dict, output_node_names, initialisation_nodes):
     tflite_graph = TFLiteGraph(filename, batch_size, feed_dict, output_node_names, initialisation_nodes)
     nng = tflite_graph.nng
     nng.refresh_after_modification()