From 3706043e9586c7c3a11ed9592bfaeb5ac9d2a27c Mon Sep 17 00:00:00 2001 From: Kristofer Jonsson Date: Tue, 28 Jun 2022 11:27:07 +0200 Subject: Add missing padding to core interface The padding is important to separate the read- and write indices by at least one cache line, to prevent cache clean and invalidation to corrupt data for the remote CPU. Change-Id: I1d50ac6c63ef4cb3e11b0c293aefaac34ac8eb1f --- kernel/ethosu_core_interface.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/kernel/ethosu_core_interface.h b/kernel/ethosu_core_interface.h index 057e3c2..193b296 100644 --- a/kernel/ethosu_core_interface.h +++ b/kernel/ethosu_core_interface.h @@ -75,10 +75,19 @@ struct ethosu_core_msg { /** * struct ethosu_core_queue_header - Message queue header + * + * The read and write indices must be separated by at least one cache line, + * else updating the read index would also overwrite the write index when + * the cache line is flushed. Because of this the message queues should be + * placed on cache line aligned addresses. + * + * The cache line length for Cortex-M is typically fixed at 32 bytes. The + * kernel driver is setup to allocated non cached memory. */ struct ethosu_core_queue_header { uint32_t size; uint32_t read; + uint32_t pad[6]; uint32_t write; }; -- cgit v1.2.1