diff options
Diffstat (limited to 'targets/corstone-300/platform.scatter')
-rw-r--r-- | targets/corstone-300/platform.scatter | 55 |
1 files changed, 53 insertions, 2 deletions
diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter index dc8f57b..fe63d01 100644 --- a/targets/corstone-300/platform.scatter +++ b/targets/corstone-300/platform.scatter @@ -18,6 +18,55 @@ * limitations under the License. */ +/* + * This is a simplified picture of the Corstone-300 memory system. + * Please refer to the Corstone SSE-300 Technical Reference Manual for + * further information. + * + * https://developer.arm.com/ip-products/subsystem/corstone/corstone-300 + * + * +---------------+ +---------------+ +------+ + * | Ethos-U55 | | Cortex-M55 +--+ ITCM | + * | | | | +------+ + * | | | | + * | | | | +------+ + * | M1 M0 | | +--+ DTCM | + * +---+-------+---+ +-------+-------+ +------+ + * | | | + * | +---+---------------+-----+ + * | | AMBA AXI NIC-400-Lite | + * | +---+-----------------+---+ + * | | | + * +---+-------+------------+ +--+-------+ + * | AMBA AXI NIC-400 | | SSE-300 | + * +---+--------+--------+--+ | SRAM | + * | | | +----------+ + * +---+---+ +--+---+ +--+--+ + * | Flash | | BRAM | | DDR | + * +-------+ +------+ +-----+ + * + * +-----------------------+-------------+-------------+----+--------------------------------------+ + * | Memory region name | Base addr | Size |IDAU| MCC load address + remarks | + * +-----------------------+-------------+-------------+----+--------------------------------------+ + * | ITCM | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB | + * | ITCM | 0x1000_0000 | 0x0008_0000 | S | Secure alias for NS ITCM | + * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0020_0000 | NS | 0x0100_0000; 2 MiB | + * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0020_0000 | S | Secure alias for NS BRAM | + * | DTCM | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each | + * | DTCM | 0x3000_0000 | 0x0008_0000 | S | Secure alias for NS DTCM | + * | SSE-300 internal SRAM | 0x2100_0000 | 0x0040_0000 | NS | 2 banks of 2 MiB each; 3cc latency) | + * | SSE-300 internal SRAM | 0x3100_0000 | 0x0040_0000 | S | Secure alias for NS internal SRAM | + * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank | + * | DDR | 0x7000_0000 | 0x1000_0000 | S | 0x0C00_0000; 256 MiB bank | + * +-----------------------+-------------+-------------+----+--------------------------------------+ + * + * Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and + * the model should only be placed in those regions. + * + * Note: Alias regions means that secure and non-secure addresses are mapped to the same physical + * memory banks. + */ + #ifndef STACK_SIZE #define STACK_SIZE 0x8000 #endif @@ -85,8 +134,9 @@ APP_IMAGE LR_START LR_SIZE #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) ; MPS3 BRAM ; Shared between Cortex-M and the NPU - BRAM BRAM_START UNINIT (BRAM_SIZE - TZ_NSC_SIZE) + BRAM BRAM_START (BRAM_SIZE - TZ_NSC_SIZE) { + * (.sram.data) } ROM_NSC TZ_NSC_START TZ_NSC_SIZE @@ -95,8 +145,9 @@ APP_IMAGE LR_START LR_SIZE } #else ; MPS3 BRAM - BRAM BRAM_START UNINIT BRAM_SIZE + BRAM BRAM_START BRAM_SIZE { + * (.sram.data) } #endif |