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author | Nir Ekhauz <nir.ekhauz@arm.com> | 2021-06-06 14:57:50 +0300 |
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committer | Nir Ekhauz <nir.ekhauz@arm.com> | 2021-09-30 18:00:25 +0300 |
commit | 3c505caf6632619df297d4448fc68e987849f6c6 (patch) | |
tree | 246507401eef481eab8786abe614bf5c0f78ab83 /targets | |
parent | 08191ead1ba93e63b07ea3b12680889ddff1c2ea (diff) | |
download | ethos-u-core-platform-3c505caf6632619df297d4448fc68e987849f6c6.tar.gz |
Add memory area to run_platform.py
Control the placement of the model and the arena for baremetal application
in SRAM/DRAM by 4 configurable options:
a. Model in SRAM and Arena in SRAM
b. Model in SRAM and Arena in DRAM
c. Model in DRAM and Arena in DRAM w/o Scratch buffer
d. Model in DRAM and Arena in DRAM with Scratch buffer in SRAM
Change-Id: Ia154be8a1c88cb13aeee62e701c2db7719a9d71c
Diffstat (limited to 'targets')
-rw-r--r-- | targets/corstone-300/CMakeLists.txt | 23 | ||||
-rw-r--r-- | targets/corstone-300/platform.ld | 27 | ||||
-rw-r--r-- | targets/corstone-300/platform.scatter | 45 |
3 files changed, 77 insertions, 18 deletions
diff --git a/targets/corstone-300/CMakeLists.txt b/targets/corstone-300/CMakeLists.txt index e5276fe..bd73481 100644 --- a/targets/corstone-300/CMakeLists.txt +++ b/targets/corstone-300/CMakeLists.txt @@ -69,10 +69,33 @@ target_compile_definitions(ethosu_target_common INTERFACE ETHOSU_PMU_EVENT_2=${ETHOSU_PMU_EVENT_2} ETHOSU_PMU_EVENT_3=${ETHOSU_PMU_EVENT_3}) +set(MEMORY_MODEL "dram" CACHE STRING "Memory config for model") +set(MEMORY_ARENA "dram" CACHE STRING "Memory config for arena") + target_compile_definitions(ethosu_target_common INTERFACE ETHOSU_NPU_TA_COUNT=${ETHOSU_TARGET_NPU_TA_COUNT} ETHOSU_NPU_COUNT=${ETHOSU_TARGET_NPU_COUNT}) +# Model memory configuration +# For ETHOSU_MODEL: 0 - SRAM, 1 - DRAM +if (MEMORY_MODEL STREQUAL "dram") + target_compile_definitions(ethosu_target_common INTERFACE + ETHOSU_MODEL=1) +else() + target_compile_definitions(ethosu_target_common INTERFACE + ETHOSU_MODEL=0) +endif() + +# Arena memory configuration +# For ETHOSU_ARENA: 0 - SRAM, 1 - DRAM +if (MEMORY_ARENA STREQUAL "dram") + target_compile_definitions(ethosu_target_common INTERFACE + ETHOSU_ARENA=1) +else() + target_compile_definitions(ethosu_target_common INTERFACE + ETHOSU_ARENA=0) +endif() + # Linker script set(LINK_FILE platform CACHE STRING "Link file") diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld index 8d44c1b..ec58acc 100644 --- a/targets/corstone-300/platform.ld +++ b/targets/corstone-300/platform.ld @@ -65,6 +65,16 @@ * memory banks. */ +#ifndef ETHOSU_MODEL + /* default value - '1', for DRAM */ + #define ETHOSU_MODEL 1 +#endif + +#ifndef ETHOSU_ARENA + /* default value - '1', for DRAM */ + #define ETHOSU_ARENA 1 +#endif + __STACK_SIZE = 0x00008000; __HEAP_SIZE = 0x00008000; @@ -239,25 +249,32 @@ SECTIONS .sram.bss : { . = ALIGN(16); -#ifdef ETHOSU_FAST_MEMORY_SIZE - *(.bss.ethosu_scratch); -#else +#if (ETHOSU_MODEL == 0) + * (network_model_sec) +#endif + +#if (ETHOSU_ARENA == 0) *(.bss.tensor_arena) #endif + + *(.bss.ethosu_scratch); *.(output_data_sec) } > SRAM :null .ddr : { -#ifdef ETHOSU_FAST_MEMORY_SIZE +#if (ETHOSU_ARENA == 1) . = ALIGN(16); *(.bss.tensor_arena) #endif + . = ALIGN(4); *(input_data_sec) . = ALIGN(16); +#if (ETHOSU_MODEL == 1) *(network_model_sec) - *(expected_output_data_sec) +#endif + * (expected_output_data_sec) } > DDR :rom_dram __eddr_data = ALIGN (16) ; diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter index 8a6bc88..fab12d1 100644 --- a/targets/corstone-300/platform.scatter +++ b/targets/corstone-300/platform.scatter @@ -65,6 +65,16 @@ * memory banks. */ +#ifndef ETHOSU_MODEL + /* default value - '1', for DRAM */ + #define ETHOSU_MODEL 1 +#endif + +#ifndef ETHOSU_ARENA + /* default value - '1', for DRAM */ + #define ETHOSU_ARENA 1 +#endif + #ifndef STACK_SIZE #define STACK_SIZE 0x8000 #endif @@ -157,14 +167,20 @@ APP_IMAGE LR_START LR_SIZE } ; 2MB SSE-300 SRAM (3 cycles read latency) from M55/U55 - SRAM SRAM_START UNINIT SRAM_SIZE + SRAM SRAM_START SRAM_SIZE { -#ifndef ETHOSU_FAST_MEMORY_SIZE - ; Place tensor arena in SRAM if we do not have a fast memory area + #if (ETHOSU_MODEL == 0) + ; Place network model in SRAM + * (network_model_sec) + #endif + + #if (ETHOSU_ARENA == 0) + ; Place tensor arena in SRAM * (.bss.tensor_arena) -#else - * (.bss.ethosu_scratch) -#endif + #endif + + ; Place scratch buffer in SRAM + * (.bss.ethosu_scratch) } ARM_LIB_HEAP (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {} @@ -185,19 +201,22 @@ LOAD_REGION_1 DDR_START DDR_SIZE { } #else //trustzone secure or non-trustzone + ; Place model and its affiliates in DRAM { + #if (ETHOSU_MODEL == 1) * (network_model_sec) + #endif * (input_data_sec) * (expected_output_data_sec) * (output_data_sec) } -#ifdef ETHOSU_FAST_MEMORY_SIZE - ; Place tensor arena in DRAM if we have a fast memory area - ARENA +0 UNINIT ALIGN 16 - { - * (.bss.tensor_arena) - } -#endif + #if (ETHOSU_ARENA == 1) + ; Place tensor arena in DRAM if we have a fast memory area + ARENA +0 UNINIT ALIGN 16 + { + * (.bss.tensor_arena) + } + #endif #endif } |