From 3c8afccabc4622a5e16a2a75474c8c9bb82f248c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Per=20=C3=85strand?= Date: Tue, 20 Oct 2020 10:29:59 +0200 Subject: Flush and invalidate data caches Implement a weak linked function to handle the data cache. If the specific device is implementing a data cache the function should be overriden with device specific implementation of the flush/invalidate functions to make sure that the cache is properly maintained with regards to the NPU DMA transaction. Change-Id: I175644ef37bee62cc77d789d2b7bc3073e72ea5a --- README.md | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index ba52525..7d6085b 100644 --- a/README.md +++ b/README.md @@ -19,6 +19,29 @@ $ cmake .. -DCMAKE_TOOLCHAIN_FILE= -DCMAKE_SYSTEM_PROCESSOR=cortex-m< $ make ``` +For running the driver on Arm CPUs which are configured with datacache, the +cache maintenance functions in the driver are exported with weakly linked +symbols that should be overriden. An example implementation using the CMSIS +primitives found in cachel1_armv7.h could be as below: + +``` +extern "C" { +void ethosu_flush_dcache(uint32_t *p, size_t bytes) { + if (p) + SCB_CleanDCache_by_Addr(p, bytes); + else + SCB_CleanDCache(); +} + +void ethosu_invalidate_dcache(uint32_t *p, size_t bytes) { + if (p) + SCB_InvalidateDCache_by_Addr(p, bytes); + else + SCB_InvalidateDCache(); +} +} +``` + # License The Arm Ethos-U Core Driver is provided under an Apache-2.0 license. Please see -- cgit v1.2.1