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author | Per Åstrand <per.astrand@arm.com> | 2020-10-20 10:29:59 +0200 |
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committer | Per Åstrand <per.astrand@arm.com> | 2020-11-16 10:53:59 +0100 |
commit | 3c8afccabc4622a5e16a2a75474c8c9bb82f248c (patch) | |
tree | 67572fe1cf6f03de25ba2f08b032129136c561d5 /README.md | |
parent | 4c94b30eb19f168a5e81e27a26c8e25bdab005b1 (diff) | |
download | ethos-u-core-driver-3c8afccabc4622a5e16a2a75474c8c9bb82f248c.tar.gz |
Flush and invalidate data caches
Implement a weak linked function to handle the data cache.
If the specific device is implementing a data cache the function should
be overriden with device specific implementation of the flush/invalidate
functions to make sure that the cache is properly maintained with
regards to the NPU DMA transaction.
Change-Id: I175644ef37bee62cc77d789d2b7bc3073e72ea5a
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 23 |
1 files changed, 23 insertions, 0 deletions
@@ -19,6 +19,29 @@ $ cmake .. -DCMAKE_TOOLCHAIN_FILE=<toolchain> -DCMAKE_SYSTEM_PROCESSOR=cortex-m< $ make ``` +For running the driver on Arm CPUs which are configured with datacache, the +cache maintenance functions in the driver are exported with weakly linked +symbols that should be overriden. An example implementation using the CMSIS +primitives found in cachel1_armv7.h could be as below: + +``` +extern "C" { +void ethosu_flush_dcache(uint32_t *p, size_t bytes) { + if (p) + SCB_CleanDCache_by_Addr(p, bytes); + else + SCB_CleanDCache(); +} + +void ethosu_invalidate_dcache(uint32_t *p, size_t bytes) { + if (p) + SCB_InvalidateDCache_by_Addr(p, bytes); + else + SCB_InvalidateDCache(); +} +} +``` + # License The Arm Ethos-U Core Driver is provided under an Apache-2.0 license. Please see |