blob: cff5eaf2ba9c51c580cb2be934ed60807cf03a5e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
//
// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#include "NeonLogicalNotWorkload.hpp"
#include "NeonWorkloadUtils.hpp"
#include <aclCommon/ArmComputeTensorHandle.hpp>
#include <aclCommon/ArmComputeTensorUtils.hpp>
#include <armnn/utility/PolymorphicDowncast.hpp>
namespace armnn
{
arm_compute::Status NeonLogicalNotWorkloadValidate(const TensorInfo& input,
const TensorInfo& output)
{
const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input);
const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output);
const arm_compute::Status aclStatus = arm_compute::NELogicalNot::validate(&aclInputInfo,
&aclOutputInfo);
return aclStatus;
}
NeonLogicalNotWorkload::NeonLogicalNotWorkload(const ElementwiseUnaryQueueDescriptor& descriptor,
const WorkloadInfo& info)
: BaseWorkload<ElementwiseUnaryQueueDescriptor>(descriptor, info)
{
m_Data.ValidateInputsOutputs("NeonLogicalNotWorkload", 1, 1);
arm_compute::ITensor& input = PolymorphicDowncast<IAclTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
arm_compute::ITensor& output = PolymorphicDowncast<IAclTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
m_LogicalNotLayer.configure(&input, &output);
}
void NeonLogicalNotWorkload::Execute() const
{
ARMNN_SCOPED_PROFILING_EVENT_NEON("NeonLogicalNotWorkload_Execute");
m_LogicalNotLayer.run();
}
} // namespace armnn
|