ArmNN
 24.02
RefL2NormalizationWorkload.cpp
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1 //
2 // Copyright © 2019-2023 Arm Ltd and Contributors. All rights reserved.
3 // SPDX-License-Identifier: MIT
4 //
5 
7 #include "RefWorkloadUtils.hpp"
8 #include "Decoders.hpp"
9 #include "Encoders.hpp"
10 
11 #include <Profiling.hpp>
12 
15 
16 #include <cmath>
17 
18 using namespace armnnUtils;
19 
20 namespace armnn
21 {
23  const L2NormalizationQueueDescriptor& descriptor,
24  const WorkloadInfo& info)
26 
28 {
30 }
31 
33 {
34  WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
35  Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
36 }
37 
38 void RefL2NormalizationWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
39 {
40  ARMNN_SCOPED_PROFILING_EVENT_REF_NAME_GUID("RefL2NormalizationWorkload_Execute");
41 
42  const TensorInfo& inputInfo = GetTensorInfo(inputs[0]);
43  const TensorInfo& outputInfo = GetTensorInfo(outputs[0]);
44 
45  auto inputDecoder = MakeDecoder<float>(inputInfo, inputs[0]->Map());
46  auto outputEncoder = MakeEncoder<float>(outputInfo, outputs[0]->Map());
47 
49 
50  const TensorShape& shape = inputInfo.GetShape();
51  unsigned int paddedShapeArray[4];
52  const int idxShift = 4 - armnn::numeric_cast<int>(shape.GetNumDimensions());
53 
54  const unsigned int batches = (idxShift == 0) ? shape[0] : 1;
55  paddedShapeArray[0] = batches;
56 
57  const int channelsIdx = armnn::numeric_cast<int>(dataLayout.GetChannelsIndex());
58  const unsigned int channels = (channelsIdx - idxShift >= 0)
59  ? shape[armnn::numeric_cast<unsigned int>(channelsIdx - idxShift)]
60  : 1;
61  paddedShapeArray[channelsIdx] = channels;
62 
63  const int heightIdx = armnn::numeric_cast<int>(dataLayout.GetHeightIndex());
64  const unsigned int height = (heightIdx - idxShift >= 0)
65  ? shape[armnn::numeric_cast<unsigned int>(heightIdx - idxShift)]
66  : 1;
67  paddedShapeArray[heightIdx] = height;
68 
69  const int widthIdx = armnn::numeric_cast<int>(dataLayout.GetWidthIndex());
70  const unsigned int width = (widthIdx - idxShift >= 0)
71  ? shape[armnn::numeric_cast<unsigned int>(widthIdx - idxShift)]
72  : 1;
73  paddedShapeArray[widthIdx] = width;
74 
75  const TensorShape& paddedShape = TensorShape(4, paddedShapeArray);
76 
77  for (unsigned int n = 0; n < batches; ++n)
78  {
79  for (unsigned int c = 0; c < channels; ++c)
80  {
81  for (unsigned int h = 0; h < height; ++h)
82  {
83  for (unsigned int w = 0; w < width; ++w)
84  {
85  float reduction = 0.0;
86  for (unsigned int d = 0; d < channels; ++d)
87  {
88  unsigned int inputIndex = dataLayout.GetIndex(paddedShape, n, d, h, w);
89 
90  (*inputDecoder)[inputIndex];
91  const float value = inputDecoder->Get();
92  reduction += value * value;
93  }
94 
95  unsigned int index = dataLayout.GetIndex(paddedShape, n, c, h, w);
96 
97  float maximum = reduction < m_Data.m_Parameters.m_Eps ? m_Data.m_Parameters.m_Eps : reduction;
98 
99  const float scale = 1.0f / sqrtf(maximum);
100 
101  (*inputDecoder)[index];
102  (*outputEncoder)[index];
103  outputEncoder->Set(inputDecoder->Get() * scale);
104  }
105  }
106  }
107  }
108 }
109 
110 } //namespace armnn
armnn::RefL2NormalizationWorkload::RefL2NormalizationWorkload
RefL2NormalizationWorkload(const L2NormalizationQueueDescriptor &descriptor, const WorkloadInfo &info)
Definition: RefL2NormalizationWorkload.cpp:22
armnn::experimental::ExecutionData::m_Data
void * m_Data
Definition: ExecutionData.hpp:16
armnn::L2NormalizationDescriptor::m_DataLayout
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
Definition: Descriptors.hpp:824
armnn::TensorInfo
Definition: Tensor.hpp:152
armnn::RefL2NormalizationWorkload::ExecuteAsync
void ExecuteAsync(ExecutionData &executionData) override
Definition: RefL2NormalizationWorkload.cpp:32
armnnUtils::DataLayoutIndexed
Provides access to the appropriate indexes for Channels, Height and Width based on DataLayout.
Definition: DataLayoutIndexed.hpp:17
Profiling.hpp
armnn::L2NormalizationQueueDescriptor
Definition: WorkloadData.hpp:358
ARMNN_SCOPED_PROFILING_EVENT_REF_NAME_GUID
#define ARMNN_SCOPED_PROFILING_EVENT_REF_NAME_GUID(label)
Creates a profiling event that uses GetGuid() and GetName() from the calling class.
Definition: RefWorkloadUtils.hpp:22
armnn::RefL2NormalizationWorkload::Execute
void Execute() const override
Definition: RefL2NormalizationWorkload.cpp:27
RefL2NormalizationWorkload.hpp
NumericCast.hpp
armnn::TensorShape
Definition: Tensor.hpp:20
armnn::QueueDescriptorWithParameters::m_Parameters
LayerDescriptor m_Parameters
Definition: WorkloadData.hpp:66
armnn::TensorShape::GetNumDimensions
unsigned int GetNumDimensions() const
Function that returns the tensor rank.
Definition: Tensor.cpp:174
armnn::WorkloadInfo
Contains information about TensorInfos of a layer.
Definition: WorkloadInfo.hpp:16
armnnUtils
Definition: CompatibleTypes.hpp:10
armnn::GetTensorInfo
const TensorInfo & GetTensorInfo(const ITensorHandle *tensorHandle)
float32 helpers
Definition: RefWorkloadUtils.hpp:33
armnn::BoostLogSeverityMapping::info
@ info
armnn::QueueDescriptor::m_Outputs
std::vector< ITensorHandle * > m_Outputs
Definition: WorkloadData.hpp:27
RefWorkloadUtils.hpp
armnn::BaseWorkload< L2NormalizationQueueDescriptor >::m_Data
L2NormalizationQueueDescriptor m_Data
Definition: Workload.hpp:89
armnn::TensorInfo::GetShape
const TensorShape & GetShape() const
Definition: Tensor.hpp:193
armnn::maximum
Definition: Maximum.hpp:13
Decoders.hpp
armnn::LayerType::Map
@ Map
armnn::experimental::WorkingMemDescriptor::m_Inputs
std::vector< ITensorHandle * > m_Inputs
Definition: WorkingMemDescriptor.hpp:20
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_quick_start.dox:6
armnn::experimental::WorkingMemDescriptor
Definition: WorkingMemDescriptor.hpp:18
armnn::L2NormalizationDescriptor::m_Eps
float m_Eps
Used to avoid dividing by zero.
Definition: Descriptors.hpp:822
Encoders.hpp
armnn::RefBaseWorkload
Definition: RefBaseWorkload.hpp:13
DataLayoutIndexed.hpp
armnn::experimental::WorkingMemDescriptor::m_Outputs
std::vector< ITensorHandle * > m_Outputs
Definition: WorkingMemDescriptor.hpp:21
armnn::QueueDescriptor::m_Inputs
std::vector< ITensorHandle * > m_Inputs
Definition: WorkloadData.hpp:26
armnn::experimental::ExecutionData
Definition: ExecutionData.hpp:14