ArmNN
 22.08
Functions
Conv2dTestImpl.hpp File Reference
#include <armnnTestUtils/LayerTestResult.hpp>
#include <ResolveType.hpp>
#include <armnn/Types.hpp>
#include <armnn/backends/IBackendInternal.hpp>
#include <armnn/backends/WorkloadFactory.hpp>

Go to the source code of this file.

Functions

template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > Convolution2d3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > Convolution2d2x3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x5Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x3Stride2x2Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x3NhwcTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
 
LayerTestResult< uint8_t, 4 > SimpleConvolution2d3x5Uint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > SimpleConvolution2d3x3Uint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > SimpleConvolution2d3x5QSymm16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > SimpleConvolution2d3x3QSymm16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution2dAsymmetricPaddingTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution1dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
 
LayerTestResult< uint8_t, 4 > Convolution1dUint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
 
LayerTestResult< float, 4 > CompareConvolution2dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory)
 
LayerTestResult< uint8_t, 4 > Convolution2dPerAxisQuantTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution2d3x3Stride2x2BFloat16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout &dataLayout)
 
LayerTestResult< float, 4 > Convolution2d3x3Stride2x2BFloat16SmallValueTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout &dataLayout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2d3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2d2x3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2dMult4Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2dMult2Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<typename T >
LayerTestResult< T, 4 > CompareDepthwiseConvolution2dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthNhwcTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthMul1Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthMul64Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dAsymmetricTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory)
 
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dUint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dDepthMul1Uint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > DepthwiseConvolution2dInt16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > DepthwiseConvolution2dDepthMul1Int16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dPerAxisQuantTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > CompareDepthwiseConvolution2dFloatTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > CompareDepthwiseConvolution2dUint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory, const armnn::DataLayout layout)
 

Function Documentation

◆ CompareConvolution2dTest()

LayerTestResult<float, 4> CompareConvolution2dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::ITensorHandleFactory &  refTensorHandleFactory 
)

Definition at line 3747 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3753 {
3754  return CompareConvolution2dTestImpl<armnn::DataType::Float32>(
3755  workloadFactory, memoryManager, refWorkloadFactory, tensorHandleFactory, refTensorHandleFactory);
3756 }

◆ CompareDepthwiseConvolution2dFloatTest()

LayerTestResult<float, 4> CompareDepthwiseConvolution2dFloatTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::ITensorHandleFactory &  refTensorHandleFactory,
const armnn::DataLayout  layout 
)

Definition at line 4039 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

4046 {
4047  return CompareDepthwiseConvolution2dTestImpl<armnn::DataType::Float32>(
4048  workloadFactory, memoryManager, refWorkloadFactory, tensorHandleFactory, refTensorHandleFactory, layout);
4049 }

◆ CompareDepthwiseConvolution2dTest()

LayerTestResult<T, 4> CompareDepthwiseConvolution2dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::ITensorHandleFactory &  refTensorHandleFactory,
const armnn::DataLayout  layout 
)

◆ CompareDepthwiseConvolution2dUint8Test()

LayerTestResult<uint8_t, 4> CompareDepthwiseConvolution2dUint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::ITensorHandleFactory &  refTensorHandleFactory,
const armnn::DataLayout  layout 
)

Definition at line 4051 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

4058 {
4059  return CompareDepthwiseConvolution2dTestImpl<armnn::DataType::QAsymmU8>(
4060  workloadFactory, memoryManager, refWorkloadFactory, tensorHandleFactory, refTensorHandleFactory, layout);
4061 }

◆ Convolution1dTest()

LayerTestResult<float, 4> Convolution1dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled 
)

Definition at line 3611 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3616 {
3617  return Convolution1dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3618  workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled);
3619 }

◆ Convolution1dUint8Test()

LayerTestResult<uint8_t, 4> Convolution1dUint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled 
)

Definition at line 3621 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3626 {
3627  return Convolution1dTestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3628  workloadFactory, memoryManager, tensorHandleFactory, 0.1f, 128, biasEnabled);
3629 }

◆ Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test()

LayerTestResult<T, 4> Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 1300 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

1306 {
1307  armnn::TensorInfo inputTensorInfo({ 1, 1, 10, 10 }, ArmnnType);
1308  std::vector<float> inputNoQuantizedValues =
1309  {
1310  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1311  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1312  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1313  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1314  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1315  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1316  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1317  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1318  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1319  1, 1, 1, 1, 1, 1, 1, 1, 1, 1
1320  };
1321 
1322  armnn::TensorInfo kernelTensorInfo({ 1, 1, 2, 2 }, ArmnnType);
1323  std::vector<float> kernelNoQuantizedValues =
1324  {
1325  1, 2,
1326  3, 4
1327  };
1328 
1329  // Since the dilation rate is 2 this will dilate the kernel to be like 3x3: d(K-1)+1 --> 2 x (2-1) + 1 = 3,
1330  // therefore the output will be 4x4: (I − K + 2P)/S +1 => trunc ( (10 - 3 + 2x2 ) / 3 + 1 )
1331  // where, dilation size = d = 2; kernel size = K = 2; input size = I = 10; padding size = P = 2; stride = S = 3
1332  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
1333  std::vector<float> outputExpectedNoQuantizedValues =
1334  {
1335  4, 7, 7, 3,
1336  6, 10, 10, 4,
1337  6, 10, 10, 4,
1338  2, 3, 3, 1
1339  };
1340  uint32_t padLeft = 1;
1341  uint32_t padTop = 1;
1342  uint32_t padRight = 1;
1343  uint32_t padBottom = 1;
1344 
1345  return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1346  workloadFactory,
1347  memoryManager,
1348  tensorHandleFactory,
1349  inputNoQuantizedValues,
1350  inputTensorInfo,
1351  kernelNoQuantizedValues,
1352  kernelTensorInfo,
1353  outputExpectedNoQuantizedValues,
1354  outputTensorInfo,
1355  2,
1356  2,
1357  layout,
1358  padLeft,
1359  padTop,
1360  padRight,
1361  padBottom,
1362  3,
1363  3,
1364  biasEnabled
1365  );
1366 }

◆ Convolution2d2x3x3Dilation3x3Test()

LayerTestResult<T, 4> Convolution2d2x3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 1227 of file Conv2dTestImpl.cpp.

1233 {
1234  armnn::TensorInfo inputTensorInfo({ 1, 2, 10, 10 }, ArmnnType);
1235  std::vector<float> inputNoQuantizedValues =
1236  {
1237  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1238  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1239  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1240  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1241  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1242  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1243  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1244  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1245  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1246  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1247 
1248  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1249  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1250  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1251  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1252  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1253  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1254  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1255  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1256  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1257  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1258  };
1259 
1260  armnn::TensorInfo kernelTensorInfo({ 1, 2, 3, 3 }, ArmnnType);
1261  std::vector<float> kernelNoQuantizedValues =
1262  {
1263  1, 2, 3,
1264  4, 5, 6,
1265  7, 8, 9,
1266 
1267  1, 2, 3,
1268  4, 5, 6,
1269  7, 8, 9
1270  };
1271 
1272  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
1273  // therefore the output will be 4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
1274  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4 }, ArmnnType);
1275  std::vector<float> outputExpectedNoQuantizedValues =
1276  {
1277  12., 10., 10., 10.,
1278  12., 10., 10., 10.,
1279  12., 10., 10., 10.,
1280  6., 4., 4., 4.
1281  };
1282 
1283  return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1284  workloadFactory,
1285  memoryManager,
1286  tensorHandleFactory,
1287  inputNoQuantizedValues,
1288  inputTensorInfo,
1289  kernelNoQuantizedValues,
1290  kernelTensorInfo,
1291  outputExpectedNoQuantizedValues,
1292  outputTensorInfo,
1293  3,
1294  3,
1295  layout,
1296  biasEnabled);
1297 }

◆ Convolution2d3x3Dilation3x3Test()

LayerTestResult<T, 4> Convolution2d3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 1169 of file Conv2dTestImpl.cpp.

1175 {
1176  armnn::TensorInfo inputTensorInfo({ 1, 1, 10, 10 }, ArmnnType);
1177  std::vector<float> inputNoQuantizedValues =
1178  {
1179  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1180  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1181  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1182  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1183  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1184  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1185  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1186  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1187  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1188  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1189  };
1190 
1191  armnn::TensorInfo kernelTensorInfo({ 1, 1, 3, 3}, ArmnnType);
1192  std::vector<float> kernelNoQuantizedValues =
1193  {
1194  1, 2, 3,
1195  4, 5, 6,
1196  7, 8, 9
1197  };
1198 
1199  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
1200  // therefore the output will be 4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
1201  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
1202  std::vector<float> outputExpectedNoQuantizedValues =
1203  {
1204  6., 5., 5., 5.,
1205  6., 5., 5., 5.,
1206  6., 5., 5., 5.,
1207  3., 2., 2., 2.
1208  };
1209 
1210  return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1211  workloadFactory,
1212  memoryManager,
1213  tensorHandleFactory,
1214  inputNoQuantizedValues,
1215  inputTensorInfo,
1216  kernelNoQuantizedValues,
1217  kernelTensorInfo,
1218  outputExpectedNoQuantizedValues,
1219  outputTensorInfo,
1220  3,
1221  3,
1222  layout,
1223  biasEnabled);
1224 }

◆ Convolution2d3x3Stride2x2BFloat16SmallValueTest()

LayerTestResult<float, 4> Convolution2d3x3Stride2x2BFloat16SmallValueTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout &  dataLayout 
)

Definition at line 1602 of file Conv2dTestImpl.cpp.

References armnn::BFloat16, armnn::Float32, armnn::IgnoreUnused(), and SimpleConvolution2dNhwcTestImpl().

Referenced by TEST_SUITE().

1608 {
1609  // BFloat16 input and weight, Float32 output
1610  armnn::IgnoreUnused(biasEnabled);
1611 
1612  // Input is a single-batch, 1 channel, 5x5 image.
1613  armnn::TensorInfo inputDesc({1, 5, 5, 1}, armnn::DataType::BFloat16);
1614 
1615  std::vector<armnn::BFloat16> inputValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1616  {
1617  0.0367984f, // 0.0368652
1618  0.0380895f, // 0.0380859
1619  0.0420157f, // 0.0419922
1620  0.0675631f, // 0.0673828
1621  0.0938920f, // 0.09375
1622  0.0476106f, // 0.0476074
1623  0.1035490f, // 0.103516
1624  0.1260370f, // 0.125977
1625  0.0461647f, // 0.0461426
1626  0.0883828f, // 0.0883789
1627  0.1159540f, // 0.115723
1628  0.0498519f, // 0.0498047
1629  0.0104630f, // 0.010437
1630  0.0154114f, // 0.0154419
1631  0.00137681f, // 0.00137329
1632  0.0344238f, // 0.0344616
1633  0.0356445f, // 0.0355693
1634  0.0495605f, // 0.0495018
1635  0.0683594f, // 0.0683308
1636  0.0991211f, // 0.0988837
1637  0.0461426f, // 0.0461838
1638  0.0996094f, // 0.0997546
1639  0.1269530f, // 0.127099
1640  0.0393066f, // 0.0392791
1641  0.103516f // 0.103641
1642  },
1643  1.0f, 0);
1644 
1645  // Use a 3x3 kernel.
1646  armnn::TensorInfo kernelDesc({1, 3, 3, 1}, armnn::DataType::BFloat16);
1647 
1648  std::vector<armnn::BFloat16> kernelValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1649  {
1650  -0.126184f, // -0.125977
1651  -0.150468f, // -0.150391
1652  -0.101412f, // -0.101562
1653  -0.0586369f,// -0.0585938
1654  -0.0865864f,// -0.0864258
1655  -0.0435089f,// -0.043457
1656  0.0347555f, // 0.034668
1657  0.0323111f, // 0.0322266
1658  0.0385381f // 0.0385742
1659  },
1660  1.0f, 0);
1661 
1662  // Expected output is a single-batch, 1 channel, 3x3 image.
1663  armnn::TensorInfo outputDesc({1, 3, 3, 1}, armnn::DataType::Float32);
1664 
1665  // Expected output (with results if calculated as FP32 in the comments)
1666  const std::vector<float> outputData =
1667  {
1668  0.000686645508f, // 0.000685
1669  0.000640869141f, // 0.000639
1670  -0.00759887695f, // -0.007631
1671  -0.02734375f, // -0.027388
1672  -0.0356445312f, // -0.035737
1673  -0.0145874023f, // -0.014568
1674  -0.0170898438f, // -0.017124
1675  -0.0373535156f, // -0.037431
1676  -0.0346679688f // -0.034808
1677  };
1678 
1679  uint32_t padLeft = 1;
1680  uint32_t padTop = 1;
1681  uint32_t padRight = 1;
1682  uint32_t padBottom = 1;
1683  uint32_t strideX = 2;
1684  uint32_t strideY = 2;
1685 
1686  return SimpleConvolution2dNhwcTestImpl
1687  <armnn::DataType::BFloat16, armnn::DataType::Float32, armnn::BFloat16, float, armnn::DataType::Float32, float>(
1688  workloadFactory,
1689  memoryManager,
1690  tensorHandleFactory,
1691  inputValues,
1692  kernelValues,
1693  std::vector<float>(),
1694  outputData,
1695  inputDesc.GetShape(),
1696  kernelDesc.GetShape(),
1697  outputDesc.GetShape(),
1698  dataLayout,
1699  1.0f,
1700  0,
1701  padLeft,
1702  padTop,
1703  padRight,
1704  padBottom,
1705  strideX,
1706  strideY);
1707 }
SimpleConvolution2dNhwcTestImpl
LayerTestResult< O, 4 > SimpleConvolution2dNhwcTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const std::vector< T > &input, const std::vector< T > &kernel, const std::vector< B > &bias, const std::vector< O > &outputExpected, const armnn::TensorShape &inputShape, const armnn::TensorShape &kernelShape, const armnn::TensorShape &outputExpectedShape, const armnn::DataLayout dataLayout, float qScale, int32_t qOffset, uint32_t padLeft=1, uint32_t padTop=1, uint32_t padRight=1, uint32_t padBottom=1, uint32_t strideX=1, uint32_t strideY=1)
Definition: Conv2dTestImpl.cpp:384
armnn::IgnoreUnused
void IgnoreUnused(Ts &&...)
Definition: IgnoreUnused.hpp:14

◆ Convolution2d3x3Stride2x2BFloat16Test()

LayerTestResult<float, 4> Convolution2d3x3Stride2x2BFloat16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout &  dataLayout 
)

Definition at line 1495 of file Conv2dTestImpl.cpp.

References armnn::BFloat16, armnn::Float32, armnn::IgnoreUnused(), and SimpleConvolution2dNhwcTestImpl().

Referenced by TEST_SUITE().

1501 {
1502  // BFloat16 input and weight, Float32 output
1503  armnn::IgnoreUnused(biasEnabled);
1504 
1505  // Input is a single-batch, 1 channel, 5x5 image.
1506  armnn::TensorInfo inputDesc({ 1, 5, 5, 1 }, armnn::DataType::BFloat16);
1507 
1508  std::vector<armnn::BFloat16> inputValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1509  {
1510  10.0367984f, // 10.0625
1511  2.0380895f, // 2.03125
1512  15.0420157f, // 15.0625
1513  22.0675631f, // 22.125
1514  8.0938920f, // 8.125
1515  5.0476106f, // 5.0625
1516  80.1035490f, // 80
1517  100.1260370f, // 100
1518  55.0461647f, // 55
1519  120.0883828f, // 120
1520  9.1159540f, // 9.125
1521  90.0498519f, // 90
1522  200.0104630f, // 200
1523  30.0154114f, // 30
1524  75.00137681f, // 75
1525  30.0344238f, // 30
1526  25.0356445f, // 25
1527  130.0495605f, // 130
1528  60.0683594f, // 60
1529  35.0991211f, // 35
1530  8.0461426f, // 8.0625
1531  12.0996094f, // 12.125
1532  98.1269530f, // 98
1533  125.0393066f, // 125
1534  5.103516f // 5.0937
1535  },
1536  1.0f, 0);
1537 
1538  // Use a 3x3 kernel.
1539  armnn::TensorInfo kernelDesc({1, 3, 3, 1}, armnn::DataType::BFloat16);
1540 
1541  std::vector<armnn::BFloat16> kernelValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1542  {
1543  -0.126184f, // -0.125977
1544  -0.150468f, // -0.150391
1545  -0.101412f, // -0.101562
1546  -0.0586369f,// -0.0585938
1547  -0.0865864f,// -0.0864258
1548  -0.0435089f,// -0.043457
1549  0.0347555f, // 0.034668
1550  0.0323111f, // 0.0322266
1551  0.0385381f // 0.0385742
1552  },
1553  1.0f, 0);
1554 
1555  // Expected output is a single-batch, 1 channel, 3x3 image.
1556  armnn::TensorInfo outputDesc({ 1, 3, 3, 1 }, armnn::DataType::Float32);
1557 
1558  // Expected output (with results if calculated as FP32 in the comments)
1559  const std::vector<float> outputData =
1560  {
1561  2.296875f, // 2.29240716
1562  5.75f, // 5.75851926
1563  3.78125f, // 3.79855026
1564  -11.625f, // -11.65498118
1565  -47.25f, // -47.27316893
1566  -30.0f, // -30.04771684
1567  -8.25f, // -8.28126168
1568  -43.5f, // -43.46531337
1569  -20.625f // -20.63477281
1570  };
1571 
1572  uint32_t padLeft = 1;
1573  uint32_t padTop = 1;
1574  uint32_t padRight = 1;
1575  uint32_t padBottom = 1;
1576  uint32_t strideX = 2;
1577  uint32_t strideY = 2;
1578 
1579  return SimpleConvolution2dNhwcTestImpl
1580  <armnn::DataType::BFloat16, armnn::DataType::Float32, armnn::BFloat16, float, armnn::DataType::Float32, float>(
1581  workloadFactory,
1582  memoryManager,
1583  tensorHandleFactory,
1584  inputValues,
1585  kernelValues,
1586  std::vector<float>(),
1587  outputData,
1588  inputDesc.GetShape(),
1589  kernelDesc.GetShape(),
1590  outputDesc.GetShape(),
1591  dataLayout,
1592  1.0f,
1593  0,
1594  padLeft,
1595  padTop,
1596  padRight,
1597  padBottom,
1598  strideX,
1599  strideY);
1600 }
SimpleConvolution2dNhwcTestImpl
LayerTestResult< O, 4 > SimpleConvolution2dNhwcTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const std::vector< T > &input, const std::vector< T > &kernel, const std::vector< B > &bias, const std::vector< O > &outputExpected, const armnn::TensorShape &inputShape, const armnn::TensorShape &kernelShape, const armnn::TensorShape &outputExpectedShape, const armnn::DataLayout dataLayout, float qScale, int32_t qOffset, uint32_t padLeft=1, uint32_t padTop=1, uint32_t padRight=1, uint32_t padBottom=1, uint32_t strideX=1, uint32_t strideY=1)
Definition: Conv2dTestImpl.cpp:384
armnn::IgnoreUnused
void IgnoreUnused(Ts &&...)
Definition: IgnoreUnused.hpp:14

◆ Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest()

LayerTestResult<float, 4> Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
armnn::DataLayout  layout 
)

Definition at line 3600 of file Conv2dTestImpl.cpp.

References Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon(), and armnn::Float32.

Referenced by TEST_SUITE().

3605 {
3606  return Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon
3607  <armnn::DataType::Float32, armnn::DataType::Float32>(
3608  workloadFactory, memoryManager, tensorHandleFactory, layout, 0.0f, 0);
3609 }
Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon
LayerTestResult< T, 4 > Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::DataLayout layout, float qScale, int32_t qOffset)
Definition: Conv2dTestImpl.cpp:944

◆ Convolution2dAsymmetricPaddingTest()

LayerTestResult<float, 4> Convolution2dAsymmetricPaddingTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
armnn::DataLayout  layout 
)

Definition at line 3590 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3595 {
3596  return SimpleConvolution2dAsymmetricPaddingTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3597  workloadFactory, memoryManager, tensorHandleFactory, layout, 0.0f, 0);
3598 }

◆ Convolution2dPerAxisQuantTest()

LayerTestResult<uint8_t, 4> Convolution2dPerAxisQuantTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::DataLayout  layout 
)

Definition at line 3631 of file Conv2dTestImpl.cpp.

References AllocateAndCopyDataToITensorHandle(), armnn::Convolution2d, CopyDataFromITensorHandle(), CopyDataToITensorHandle(), ITensorHandleFactory::CreateTensorHandle(), IWorkloadFactory::CreateWorkload(), QueueDescriptorWithParameters< LayerDescriptor >::m_Parameters, Convolution2dDescriptor::m_StrideX, armnn::NCHW, and PermuteTensorNhwcToNchw().

Referenced by TEST_SUITE().

3636 {
3637  using namespace armnn;
3638 
3639  const DataType inputType = DataType::QAsymmU8;
3640  const DataType kernelType = DataType::QSymmS8;
3641  const DataType biasType = DataType::Signed32;
3642 
3643  TensorInfo inputInfo ({ 1, 3, 1, 2 }, inputType, 0.5f, 128);
3644  TensorInfo outputInfo({ 1, 3, 1, 3 }, inputType, 1.0f, 128);
3645 
3646  const std::vector<float> quantScales{ 0.5f, 0.75f, 1.0f };
3647  constexpr unsigned int quantDimension = 0;
3648 
3649  TensorInfo kernelInfo({ 3, 1, 1, 2 }, kernelType, quantScales, quantDimension);
3650 
3651  const std::vector<float> biasQuantScales{ 0.25f, 0.375f, 0.5f };
3652  TensorInfo biasInfo({ 3 }, biasType, biasQuantScales, quantDimension);
3653 
3654  std::vector<uint8_t> inputData =
3655  {
3656  138, 108, 138, 108, 138, 108
3657  };
3658 
3659  std::vector<int8_t> kernelData =
3660  {
3661  1, 2, 1, 2, 1, 2
3662  };
3663 
3664  std::vector<int32_t> biasData =
3665  {
3666  4, 4, 4
3667  };
3668 
3669  std::vector<uint8_t> expectedOutputData =
3670  {
3671  121, 118, 115, 121, 118, 115, 121, 118, 115
3672  };
3673 
3674  if (layout == DataLayout::NCHW)
3675  {
3676  PermuteTensorNhwcToNchw(inputInfo, inputData);
3677  PermuteTensorNhwcToNchw(kernelInfo, kernelData);
3678  PermuteTensorNhwcToNchw(outputInfo, expectedOutputData);
3679  }
3680 
3681  std::vector<uint8_t> actualOutput(outputInfo.GetNumElements());
3682 
3683  Convolution2dDescriptor descriptor;
3684  descriptor.m_StrideX = 1;
3685  descriptor.m_StrideY = 1;
3686  descriptor.m_PadLeft = 0;
3687  descriptor.m_PadRight = 0;
3688  descriptor.m_PadTop = 0;
3689  descriptor.m_PadBottom = 0;
3690  descriptor.m_BiasEnabled = true;
3691  descriptor.m_DataLayout = layout;
3692 
3693  std::unique_ptr<ITensorHandle> inputHandle = tensorHandleFactory.CreateTensorHandle(inputInfo);
3694  std::unique_ptr<ITensorHandle> outputHandle = tensorHandleFactory.CreateTensorHandle(outputInfo);
3695  std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.CreateTensorHandle(kernelInfo);
3696  std::unique_ptr<armnn::ITensorHandle> biasHandle = nullptr;
3697 
3698  WorkloadInfo workloadInfo;
3699  ScopedTensorHandle weightTensor(kernelInfo);
3700  ScopedTensorHandle biasTensor(biasInfo);
3701 
3702  AllocateAndCopyDataToITensorHandle(&weightTensor, kernelData.data());
3703  AllocateAndCopyDataToITensorHandle(&biasTensor, biasData.data());
3704 
3705  Convolution2dQueueDescriptor queueDescriptor;
3706  queueDescriptor.m_Parameters = descriptor;
3707  queueDescriptor.m_Weight = &weightTensor;
3708  queueDescriptor.m_Bias = &biasTensor;
3709 
3710  AddInputToWorkload(queueDescriptor, workloadInfo, inputInfo, inputHandle.get());
3711  AddInputToWorkload(queueDescriptor, workloadInfo, kernelInfo, weightsHandle.get());
3712 
3713  if (descriptor.m_BiasEnabled)
3714  {
3715  biasHandle = tensorHandleFactory.CreateTensorHandle(biasInfo);
3716  AddInputToWorkload(queueDescriptor, workloadInfo, biasInfo, biasHandle.get());
3717  }
3718 
3719  AddOutputToWorkload(queueDescriptor, workloadInfo, outputInfo, outputHandle.get());
3720 
3721  std::unique_ptr<IWorkload> workload= workloadFactory.CreateWorkload(armnn::LayerType::Convolution2d,
3722  queueDescriptor,
3723  workloadInfo);
3724  inputHandle->Allocate();
3725  outputHandle->Allocate();
3726  weightsHandle->Allocate();
3727 
3728  if (descriptor.m_BiasEnabled)
3729  {
3730  biasHandle->Allocate();
3731  CopyDataToITensorHandle(biasHandle.get(), biasData.data());
3732  }
3733  CopyDataToITensorHandle(inputHandle.get(), inputData.data());
3734  CopyDataToITensorHandle(weightsHandle.get(), kernelData.data());
3735 
3736 
3737  ExecuteWorkload(*workload, memoryManager);
3738 
3739  CopyDataFromITensorHandle(actualOutput.data(), outputHandle.get());
3740 
3741  return LayerTestResult<uint8_t, 4>(actualOutput,
3742  expectedOutputData,
3743  outputHandle->GetShape(),
3744  outputInfo.GetShape());
3745 }
PermuteTensorNhwcToNchw
void PermuteTensorNhwcToNchw(armnn::TensorInfo &tensorInfo, std::vector< T > &tensorData)
Definition: DataLayoutUtils.hpp:26
armnn::Convolution2dDescriptor
A Convolution2dDescriptor for the Convolution2dLayer.
Definition: Descriptors.hpp:495
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_quick_start.dox:6
AllocateAndCopyDataToITensorHandle
void AllocateAndCopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:19
armnn::Convolution2dDescriptor::m_StrideX
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
Definition: Descriptors.hpp:535
armnn::DataType
DataType
Definition: Types.hpp:48
CopyDataFromITensorHandle
void CopyDataFromITensorHandle(void *mem, const armnn::ITensorHandle *tensorHandle)
Definition: TensorCopyUtils.cpp:14
CopyDataToITensorHandle
void CopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:9
armnn::WorkloadInfo
Contains information about TensorInfos of a layer.
Definition: WorkloadInfo.hpp:16
armnn::IWorkloadFactory::CreateWorkload
virtual std::unique_ptr< IWorkload > CreateWorkload(LayerType type, const QueueDescriptor &descriptor, const WorkloadInfo &info) const
Definition: WorkloadFactory.cpp:1575
armnn::ITensorHandleFactory::CreateTensorHandle
virtual std::unique_ptr< ITensorHandle > CreateTensorHandle(const TensorInfo &tensorInfo) const =0

◆ DepthwiseConvolution2d2x3x3Dilation3x3Test()

LayerTestResult<T, 4> DepthwiseConvolution2d2x3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2879 of file Conv2dTestImpl.cpp.

2885 {
2886  armnn::TensorInfo inputTensorInfo({1, 2, 10, 10}, ArmnnType);
2887  std::vector<float> inputNoQuantizedValues =
2888  {
2889  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2890  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2891  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2892  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2893  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2894  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2895  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2896  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2897  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2898  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2899 
2900  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2901  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2902  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2903  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2904  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2905  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2906  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2907  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2908  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2909  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2910  };
2911 
2912  armnn::TensorInfo kernelTensorInfo({ 1, 3, 3, 2}, ArmnnType);
2913  std::vector<float> kernelNoQuantizedValues =
2914  {
2915  1, 2, 3,
2916  4, 5, 6,
2917  7, 8, 9,
2918 
2919  1, 2, 3,
2920  4, 5, 6,
2921  7, 8, 9
2922  };
2923 
2924  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
2925  // therefore the output will be 2x4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
2926  armnn::TensorInfo outputTensorInfo({ 1, 2, 4, 4}, ArmnnType);
2927  std::vector<float> outputExpectedNoQuantizedValues =
2928  {
2929  2, 9, 9, 9, 2, 9, 9, 9, 2, 9, 9, 9, 5, 3, 3, 3, 3,
2930 
2931  1, 1, 1, 3, 1, 1, 1, 3, 1, 1, 1, 6, 4, 4, 4
2932  };
2933 
2934  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2935  workloadFactory,
2936  memoryManager,
2937  tensorHandleFactory,
2938  inputNoQuantizedValues,
2939  inputTensorInfo,
2940  kernelNoQuantizedValues,
2941  kernelTensorInfo,
2942  outputExpectedNoQuantizedValues,
2943  outputTensorInfo,
2944  3,
2945  3,
2946  layout,
2947  biasEnabled);
2948 }

◆ DepthwiseConvolution2d3x3Dilation3x3Test()

LayerTestResult<T, 4> DepthwiseConvolution2d3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2821 of file Conv2dTestImpl.cpp.

2827 {
2828  armnn::TensorInfo inputTensorInfo({1, 1, 10, 10}, ArmnnType);
2829  std::vector<float> inputNoQuantizedValues =
2830  {
2831  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2832  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2833  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2834  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2835  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2836  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2837  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2838  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2839  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2840  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2841  };
2842 
2843  armnn::TensorInfo kernelTensorInfo({ 1, 3, 3, 1}, ArmnnType);
2844  std::vector<float> kernelNoQuantizedValues =
2845  {
2846  1, 2, 3,
2847  4, 5, 6,
2848  7, 8, 9
2849  };
2850 
2851  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
2852  // therefore the output will be 4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
2853  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
2854  std::vector<float> outputExpectedNoQuantizedValues =
2855  {
2856  6., 5., 5., 5.,
2857  6., 5., 5., 5.,
2858  6., 5., 5., 5.,
2859  3., 2., 2., 2.
2860  };
2861 
2862  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2863  workloadFactory,
2864  memoryManager,
2865  tensorHandleFactory,
2866  inputNoQuantizedValues,
2867  inputTensorInfo,
2868  kernelNoQuantizedValues,
2869  kernelTensorInfo,
2870  outputExpectedNoQuantizedValues,
2871  outputTensorInfo,
2872  3,
2873  3,
2874  layout,
2875  biasEnabled);
2876 }

◆ DepthwiseConvolution2dAsymmetricTest()

LayerTestResult<float, 4> DepthwiseConvolution2dAsymmetricTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3833 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3839 {
3840  return DepthwiseConvolution2dAsymmetricTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3841  workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled, layout);
3842 }

◆ DepthwiseConvolution2dDepthMul1Int16Test()

LayerTestResult<int16_t, 4> DepthwiseConvolution2dDepthMul1Int16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3891 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3897 {
3898  return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3899  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3900 }

◆ DepthwiseConvolution2dDepthMul1Test()

LayerTestResult<float, 4> DepthwiseConvolution2dDepthMul1Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3779 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3785 {
3786  return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3787  workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled, layout);
3788 }

◆ DepthwiseConvolution2dDepthMul1Uint8Test()

LayerTestResult<uint8_t, 4> DepthwiseConvolution2dDepthMul1Uint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3855 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3861 {
3862  return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3863  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3864 }

◆ DepthwiseConvolution2dDepthMul64Test()

LayerTestResult<float, 4> DepthwiseConvolution2dDepthMul64Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory 
)

Definition at line 3790 of file Conv2dTestImpl.cpp.

References armnn::Float32, armnn::GetDataTypeSize(), armnn::NCHW, armnnUtils::Permute(), and armnnUtils::Permuted().

Referenced by TEST_SUITE().

3794 {
3795  armnn::TensorInfo inputTensorInfo({ 1, 1, 2, 2 }, armnn::DataType::Float32);
3796  std::vector<float> input = { 1.f, 2.f, 3.f, 4.f };
3797 
3798  std::vector<float> kernelData;
3799  std::vector<float> singleDepthKernel{ 1.f, -1.f, -1.f, 1.f };
3800  for (unsigned int i = 0; i < 64; ++i)
3801  {
3802  kernelData.insert(kernelData.end(), singleDepthKernel.begin(), singleDepthKernel.end());
3803  }
3804  armnn::TensorInfo kernelTensorInfo({ 64, 1, 2, 2 }, armnn::DataType::Float32);
3805 
3806  // permute from [O,1,H,W] --> [1,H,W,O]
3807  armnn::PermutationVector permutationVector {3,0,1,2};
3808  kernelTensorInfo = armnnUtils::Permuted(kernelTensorInfo, permutationVector);
3809  std::vector<float> kernelPermuted(kernelTensorInfo.GetNumElements());
3810  armnnUtils::Permute(kernelTensorInfo.GetShape(), permutationVector,
3811  kernelData.data(), kernelPermuted.data(),
3812  GetDataTypeSize(kernelTensorInfo.GetDataType()));
3813 
3814  std::vector<float> expectedOutputData(64, 0.f);
3815  armnn::TensorInfo outputTensorInfo({ 1, 64, 1, 1 }, armnn::DataType::Float32);
3816 
3817  return DepthwiseConvolution2dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3818  workloadFactory,
3819  memoryManager,
3820  tensorHandleFactory,
3821  input,
3822  kernelPermuted,
3823  std::vector<float>(),
3824  expectedOutputData,
3825  inputTensorInfo.GetShape(),
3826  kernelTensorInfo.GetShape(),
3827  outputTensorInfo.GetShape(),
3828  0.f,
3829  0,
3830  armnn::DataLayout::NCHW);
3831 }
armnnUtils::Permute
void Permute(const armnn::TensorShape &dstShape, const armnn::PermutationVector &mappings, const void *src, void *dst, size_t dataTypeSize)
Definition: Permute.cpp:131
armnnUtils::Permuted
armnn::TensorShape Permuted(const armnn::TensorShape &srcShape, const armnn::PermutationVector &mappings)
Definition: Permute.cpp:98
armnn::GetDataTypeSize
constexpr unsigned int GetDataTypeSize(DataType dataType)
Definition: TypesUtils.hpp:151

◆ DepthwiseConvolution2dDepthNhwcTest()

LayerTestResult<float, 4> DepthwiseConvolution2dDepthNhwcTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled 
)

Definition at line 3769 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3774 {
3775  return DepthwiseConvolution2dNhwcTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3776  workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled);
3777 }

◆ DepthwiseConvolution2dInt16Test()

LayerTestResult<int16_t, 4> DepthwiseConvolution2dInt16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3880 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3886 {
3887  return DepthwiseConvolution2dTestImpl<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3888  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3889 }

◆ DepthwiseConvolution2dMult2Test()

LayerTestResult<T, 4> DepthwiseConvolution2dMult2Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3026 of file Conv2dTestImpl.cpp.

3032 {
3033  armnn::TensorInfo inputTensorInfo({1, 2, 3, 3}, ArmnnType);
3034  std::vector<float> inputNoQuantizedValues =
3035  {
3036  10.0, 10.0, 10.0,
3037  10.0, 10.0, 10.0,
3038  10.0, 10.0, 10.0,
3039 
3040  21.0, 22.0, 23.0,
3041  24.0, 25.0, 26.0,
3042  27.0, 28.0, 29.0
3043  };
3044 
3045  armnn::TensorInfo kernelTensorInfo({ 1, 2, 2, 4}, ArmnnType);
3046 
3047  std::vector<float> kernelNoQuantizedValues =
3048  {
3049  0.25f, 0.25f,
3050  0.25f, 0.25f,
3051 
3052  0.2f , 0.0f,
3053  0.0f , 0.0f,
3054 
3055  0.0f , 0.0f,
3056  0.0f , 0.1f,
3057 
3058  0.0f , 0.3f,
3059  0.0f , 0.0f
3060 
3061  };
3062 
3063  armnn::TensorInfo outputTensorInfo({ 1, 4, 2, 2}, ArmnnType);
3064  std::vector<float> outputExpectedNoQuantizedValues =
3065  {
3066  4.5f, 4.5f, 4.5f, 4.5f,
3067  5.5f, 5.5f, 5.5f, 5.5f,
3068  5.25f, 5.5f, 6.0f, 6.25f,
3069  7.65f, 8.0f, 8.7f, 9.05f
3070  };
3071 
3072 
3073  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
3074  workloadFactory,
3075  memoryManager,
3076  tensorHandleFactory,
3077  inputNoQuantizedValues,
3078  inputTensorInfo,
3079  kernelNoQuantizedValues,
3080  kernelTensorInfo,
3081  outputExpectedNoQuantizedValues,
3082  outputTensorInfo,
3083  1,
3084  1,
3085  layout,
3086  biasEnabled);
3087 }

◆ DepthwiseConvolution2dMult4Test()

LayerTestResult<T, 4> DepthwiseConvolution2dMult4Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2951 of file Conv2dTestImpl.cpp.

2957 {
2958  armnn::TensorInfo inputTensorInfo({1, 2, 3, 3}, ArmnnType);
2959  std::vector<float> inputNoQuantizedValues =
2960  {
2961  10.0, 10.0, 10.0,
2962  10.0, 10.0, 10.0,
2963  10.0, 10.0, 10.0,
2964 
2965  21.0, 22.0, 23.0,
2966  24.0, 25.0, 26.0,
2967  27.0, 28.0, 29.0
2968  };
2969 
2970  armnn::TensorInfo kernelTensorInfo({ 1, 2, 2, 8}, ArmnnType);
2971 
2972  std::vector<float> kernelNoQuantizedValues =
2973  {
2974  0.25f, 0.25f,
2975  0.25f, 0.25f,
2976 
2977  0.25f, 0.25f,
2978  0.25f, 0.25f,
2979 
2980  0.0f , 0.0f,
2981  0.0f , 0.1f,
2982 
2983  0.0f , 0.0f,
2984  0.0f , 0.1f,
2985 
2986  0.2f , 0.0f,
2987  0.0f , 0.0f,
2988 
2989  0.2f , 0.0f,
2990  0.0f , 0.0f,
2991 
2992  0.0f , 0.3f,
2993  0.0f , 0.0f,
2994 
2995  0.0f , 0.3f,
2996  0.0f , 0.0f
2997  };
2998 
2999  armnn::TensorInfo outputTensorInfo({ 1, 8, 2, 2}, ArmnnType);
3000  std::vector<float> outputExpectedNoQuantizedValues =
3001  {
3002  4.5f, 4.5f, 4.5f, 4.5f, 5.5f, 5.5f, 5.5f, 5.5f,
3003  2.5f, 2.5f, 2.5f, 2.5f, 3.5f, 3.5f, 3.5f, 3.5f,
3004  10.05f, 10.5f, 11.4f, 11.85f, 12.75f, 13.3f, 14.4f, 14.95f,
3005  5.25f, 5.5f, 6.0f, 6.25f, 7.45f, 7.8f, 8.5f, 8.85f
3006  };
3007 
3008 
3009  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
3010  workloadFactory,
3011  memoryManager,
3012  tensorHandleFactory,
3013  inputNoQuantizedValues,
3014  inputTensorInfo,
3015  kernelNoQuantizedValues,
3016  kernelTensorInfo,
3017  outputExpectedNoQuantizedValues,
3018  outputTensorInfo,
3019  1,
3020  1,
3021  layout,
3022  biasEnabled);
3023 }

◆ DepthwiseConvolution2dPerAxisQuantTest()

LayerTestResult<uint8_t, 4> DepthwiseConvolution2dPerAxisQuantTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::DataLayout  layout 
)

Definition at line 3902 of file Conv2dTestImpl.cpp.

References AllocateAndCopyDataToITensorHandle(), CopyDataFromITensorHandle(), CopyDataToITensorHandle(), ITensorHandleFactory::CreateTensorHandle(), IWorkloadFactory::CreateWorkload(), armnn::DepthwiseConvolution2d, IWorkloadFactory::GetBackendId(), DepthwiseConvolution2dQueueDescriptor::m_Bias, QueueDescriptorWithParameters< LayerDescriptor >::m_Parameters, DepthwiseConvolution2dDescriptor::m_StrideX, DepthwiseConvolution2dQueueDescriptor::m_Weight, armnn::NCHW, armnnUtils::Permute(), armnnUtils::Permuted(), PermuteTensorNhwcToNchw(), and TensorInfo::SetShape().

Referenced by TEST_SUITE().

3907 {
3908  using namespace armnn;
3909 
3910  const DataType inputType = DataType::QAsymmU8;
3911  const DataType kernelType = DataType::QSymmS8;
3912  const DataType biasType = DataType::Signed32;
3913 
3914  TensorInfo inputInfo ({ 1, 3, 3, 2 }, inputType, 0.5f, 128); // N H W C
3915  TensorInfo outputInfo({ 1, 2, 2, 4 }, inputType, 1.0f, 128); // N H W C
3916 
3917  const std::vector<float> quantScales{ 1.0f, 0.5f, 1.0f, 0.5f };
3918  const unsigned int quantDimension = 3;
3919  TensorInfo kernelInfo({ 1, 2, 2, 4 }, kernelType, quantScales, quantDimension); // [1, H, W, I*M]
3920 
3921  const std::vector<float> biasQuantScales{ 0.5f, 0.25f, 0.5f, 0.25f };
3922  constexpr unsigned int biasQuantDimension = 0;
3923  TensorInfo biasInfo({ 4 }, biasType, biasQuantScales, biasQuantDimension);
3924 
3925  std::vector<uint8_t> inputData =
3926  {
3927  129, 130,
3928  129, 130,
3929  129, 130,
3930  129, 130,
3931  129, 130,
3932  129, 130,
3933  129, 130,
3934  129, 130,
3935  129, 130
3936  };
3937 
3938  std::vector<int8_t> kernelData =
3939  {
3940  1, 1, 1, 1,
3941  1, 1, 1, 1,
3942  1, 1, 1, 1,
3943  1, 1, 1, 1
3944  };
3945 
3946  if (workloadFactory.GetBackendId() == armnn::BackendId("GpuAcc") ||
3947  workloadFactory.GetBackendId() == armnn::BackendId("CpuAcc"))
3948  {
3949  if (layout == armnn::DataLayout::NCHW)
3950  {
3951  std::vector<int8_t> tmp(kernelData.size());
3952  kernelInfo.SetShape(armnnUtils::Permuted(kernelInfo.GetShape(), {0, 2, 3, 1}));
3953  armnnUtils::Permute(kernelInfo.GetShape(), {0, 2, 3, 1}, kernelData.data(), tmp.data(), sizeof(int8_t));
3954  kernelData = tmp;
3955  }
3956  }
3957 
3958  std::vector<int32_t> biasData =
3959  {
3960  4, 4, 4, 4
3961  };
3962 
3963  std::vector<uint8_t> expectedOutputData =
3964  {
3965  132, 130, 134, 131,
3966  132, 130, 134, 131,
3967  132, 130, 134, 131,
3968  132, 130, 134, 131
3969  };
3970 
3971  if (layout == DataLayout::NCHW)
3972  {
3973  PermuteTensorNhwcToNchw(inputInfo, inputData);
3974  PermuteTensorNhwcToNchw(outputInfo, expectedOutputData);
3975  }
3976 
3977  std::vector<uint8_t> actualOutput(outputInfo.GetNumElements());
3978 
3979  DepthwiseConvolution2dDescriptor descriptor;
3980  descriptor.m_StrideX = 1;
3981  descriptor.m_StrideY = 1;
3982  descriptor.m_PadLeft = 0;
3983  descriptor.m_PadRight = 0;
3984  descriptor.m_PadTop = 0;
3985  descriptor.m_PadBottom = 0;
3986  descriptor.m_DilationX = 1;
3987  descriptor.m_DilationY = 1;
3988  descriptor.m_BiasEnabled = true;
3989  descriptor.m_DataLayout = layout;
3990 
3991  std::unique_ptr<ITensorHandle> inputHandle = tensorHandleFactory.CreateTensorHandle(inputInfo);
3992  std::unique_ptr<ITensorHandle> weightsHandle = tensorHandleFactory.CreateTensorHandle(kernelInfo);
3993  std::unique_ptr<ITensorHandle> biasHandle = tensorHandleFactory.CreateTensorHandle(biasInfo);
3994  std::unique_ptr<ITensorHandle> outputHandle = tensorHandleFactory.CreateTensorHandle(outputInfo);
3995 
3996  DepthwiseConvolution2dQueueDescriptor queueDescriptor;
3997  WorkloadInfo workloadInfo;
3998  ScopedTensorHandle weightTensor(kernelInfo);
3999  ScopedTensorHandle biasTensor(biasInfo);
4000 
4001  AddInputToWorkload(queueDescriptor, workloadInfo, inputInfo, inputHandle.get());
4002  AddInputToWorkload(queueDescriptor, workloadInfo, kernelInfo, weightsHandle.get());
4003  AddOutputToWorkload(queueDescriptor, workloadInfo, outputInfo, outputHandle.get());
4004  AddInputToWorkload(queueDescriptor, workloadInfo, biasInfo, biasHandle.get());
4005 
4006  // AllocateAndCopyDataToITensorHandle() is required twice for the weights AND biases:
4007  // See comment in DepthwiseConvolution2dAsymmetricTestImpl() for reasons.
4008  // 1) ScopedTensorHandle (weightsTensor) required for QueueDescriptor (data.m_Weight).
4009  // 2) ITensorHandle (converts to Backend TensorHandle) required in RefWorkload for GetTensorInfo() method.
4010  AllocateAndCopyDataToITensorHandle(weightsHandle.get(), kernelData.data());
4011  AllocateAndCopyDataToITensorHandle(&weightTensor, kernelData.data());
4012  AllocateAndCopyDataToITensorHandle(biasHandle.get(), biasData.data());
4013  AllocateAndCopyDataToITensorHandle(&biasTensor, biasData.data());
4014 
4015  queueDescriptor.m_Parameters = descriptor;
4016  queueDescriptor.m_Weight = &weightTensor;
4017  queueDescriptor.m_Bias = &biasTensor;
4018 
4019  std::unique_ptr<IWorkload> workload = workloadFactory.CreateWorkload(armnn::LayerType::DepthwiseConvolution2d,
4020  queueDescriptor,
4021  workloadInfo);
4022  inputHandle->Allocate();
4023  outputHandle->Allocate();
4024 
4025  CopyDataToITensorHandle(inputHandle.get(), inputData.data());
4026 
4027  ExecuteWorkload(*workload, memoryManager);
4028 
4029  LayerTestResult<uint8_t, 4> ret(outputInfo);
4030 
4031  CopyDataFromITensorHandle(actualOutput.data(), outputHandle.get());
4032 
4033  return LayerTestResult<uint8_t, 4>(actualOutput,
4034  expectedOutputData,
4035  outputHandle->GetShape(),
4036  outputInfo.GetShape());
4037 }
armnn::IWorkloadFactory::GetBackendId
virtual const BackendId & GetBackendId() const =0
PermuteTensorNhwcToNchw
void PermuteTensorNhwcToNchw(armnn::TensorInfo &tensorInfo, std::vector< T > &tensorData)
Definition: DataLayoutUtils.hpp:26
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_quick_start.dox:6
AllocateAndCopyDataToITensorHandle
void AllocateAndCopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:19
armnn::TensorInfo::SetShape
void SetShape(const TensorShape &newShape)
Definition: Tensor.hpp:193
armnn::DepthwiseConvolution2dDescriptor::m_StrideX
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
Definition: Descriptors.hpp:661
armnn::DataType
DataType
Definition: Types.hpp:48
CopyDataFromITensorHandle
void CopyDataFromITensorHandle(void *mem, const armnn::ITensorHandle *tensorHandle)
Definition: TensorCopyUtils.cpp:14
CopyDataToITensorHandle
void CopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:9
armnn::WorkloadInfo
Contains information about TensorInfos of a layer.
Definition: WorkloadInfo.hpp:16
armnn::IWorkloadFactory::CreateWorkload
virtual std::unique_ptr< IWorkload > CreateWorkload(LayerType type, const QueueDescriptor &descriptor, const WorkloadInfo &info) const
Definition: WorkloadFactory.cpp:1575
armnnUtils::Permuted
armnn::TensorShape Permuted(const armnn::TensorShape &srcShape, const armnn::PermutationVector &mappings)
Definition: Permute.cpp:98
armnn::ITensorHandleFactory::CreateTensorHandle
virtual std::unique_ptr< ITensorHandle > CreateTensorHandle(const TensorInfo &tensorInfo) const =0
armnn::DepthwiseConvolution2dDescriptor
A DepthwiseConvolution2dDescriptor for the DepthwiseConvolution2dLayer.
Definition: Descriptors.hpp:620
armnn::DepthwiseConvolution2dQueueDescriptor
Depthwise Convolution 2D layer workload data.
Definition: WorkloadData.hpp:247

◆ DepthwiseConvolution2dTest()

LayerTestResult<float, 4> DepthwiseConvolution2dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3758 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3764 {
3765  return DepthwiseConvolution2dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3766  workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled, layout);
3767 }

◆ DepthwiseConvolution2dUint8Test()

LayerTestResult<uint8_t, 4> DepthwiseConvolution2dUint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3844 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3850 {
3851  return DepthwiseConvolution2dTestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3852  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3853 }

◆ SimpleConvolution2d3x3NhwcTest()

LayerTestResult<float, 4> SimpleConvolution2d3x3NhwcTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled 
)

Definition at line 3524 of file Conv2dTestImpl.cpp.

References armnn::NHWC.

Referenced by TEST_SUITE().

3529 {
3530  return SimpleConvolution2d3x3NhwcTestCommon<armnn::DataType::Float32>(
3531  workloadFactory,
3532  memoryManager,
3533  tensorHandleFactory,
3534  0.f,
3535  0,
3536  biasEnabled,
3537  armnn::DataLayout::NHWC);
3538 }

◆ SimpleConvolution2d3x3QSymm16Test()

LayerTestResult<int16_t, 4> SimpleConvolution2d3x3QSymm16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3579 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3585 {
3586  return SimpleConvolution2d3x3TestCommon<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3587  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3588 }

◆ SimpleConvolution2d3x3Stride2x2Test()

LayerTestResult<float, 4> SimpleConvolution2d3x3Stride2x2Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3540 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3546 {
3547  return SimpleConvolution2d3x3Stride2x2TestCommon<armnn::DataType::Float32>(
3548  workloadFactory,
3549  memoryManager,
3550  tensorHandleFactory,
3551  0.f,
3552  0,
3553  biasEnabled,
3554  layout);
3555 }

◆ SimpleConvolution2d3x3Test()

LayerTestResult<float, 4> SimpleConvolution2d3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3513 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3519 {
3520  return SimpleConvolution2d3x3TestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3521  workloadFactory, memoryManager, tensorHandleFactory, 0.f, 0, biasEnabled, layout);
3522 }

◆ SimpleConvolution2d3x3Uint8Test()

LayerTestResult<uint8_t, 4> SimpleConvolution2d3x3Uint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3557 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3563 {
3564  return SimpleConvolution2d3x3TestCommon<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3565  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3566 }

◆ SimpleConvolution2d3x5QSymm16Test()

LayerTestResult<int16_t, 4> SimpleConvolution2d3x5QSymm16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3568 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3574 {
3575  return SimpleConvolution2d3x5TestCommon<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3576  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3577 }

◆ SimpleConvolution2d3x5Test()

LayerTestResult<float, 4> SimpleConvolution2d3x5Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3491 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3497 {
3498  return SimpleConvolution2d3x5TestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3499  workloadFactory, memoryManager, tensorHandleFactory, 0.f, 0, biasEnabled, layout);
3500 }

◆ SimpleConvolution2d3x5Uint8Test()

LayerTestResult<uint8_t, 4> SimpleConvolution2d3x5Uint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3502 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3508 {
3509  return SimpleConvolution2d3x5TestCommon<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3510  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3511 }

◆ SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTest()

LayerTestResult<float, 4> SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory 
)

Definition at line 3866 of file Conv2dTestImpl.cpp.

Referenced by TEST_SUITE().

3870 {
3871  return SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3872  workloadFactory,
3873  memoryManager,
3874  tensorHandleFactory,
3875  0.f,
3876  0,
3877  false);
3878 }