ArmNN
 22.05
RefConvolution2dWorkload.cpp
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1 //
2 // Copyright © 2017 Arm Ltd. All rights reserved.
3 // SPDX-License-Identifier: MIT
4 //
5 
7 
8 #include "ConvImpl.hpp"
9 #include "RefWorkloadUtils.hpp"
10 
11 #include "Profiling.hpp"
12 
13 namespace armnn
14 {
16  const WorkloadInfo& info)
18  , m_InputShape(info.m_InputTensorInfos[0].GetShape())
19  , m_FilterShape(info.m_InputTensorInfos[1].GetShape())
20  , m_OutputShape(info.m_OutputTensorInfos[0].GetShape())
21 {
22  WorkloadInfo detailsInfo;
23  detailsInfo.m_InputTensorInfos = info.m_InputTensorInfos;
24  detailsInfo.m_OutputTensorInfos = info.m_OutputTensorInfos;
25 
26  // Report Profiling Details
27  ARMNN_REPORT_PROFILING_WORKLOAD_DESC("RefConvolution2dWorkload_Construct",
28  descriptor.m_Parameters,
29  detailsInfo,
30  this->GetGuid());
31 }
32 
34 {
36 }
37 
39 {
40  Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
41 }
42 
43 void RefConvolution2dWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
44 {
45  ARMNN_SCOPED_PROFILING_EVENT_GUID(Compute::CpuRef, "RefConvolution2dWorkload_Execute", this->GetGuid());
46 
47  std::unique_ptr<Decoder<float>> inputDecoder = MakeDecoder<float>(GetTensorInfo(inputs[0]), inputs[0]->Map());
48  std::unique_ptr<Encoder<float>> outputEncoder = MakeEncoder<float>(GetTensorInfo(outputs[0]), outputs[0]->Map());
49 
50  std::unique_ptr<Decoder<float>> weightsDecoder = MakeDecoder<float>(GetTensorInfo(inputs[1]), inputs[1]->Map());
51  std::unique_ptr<Decoder<float>> biasDecoder;
52 
54  {
55  biasDecoder = MakeDecoder<float>(GetTensorInfo(inputs[2]), inputs[2]->Map());
56  }
57 
58  Convolve(m_InputShape, *inputDecoder, m_OutputShape, *outputEncoder, m_FilterShape,
59  *weightsDecoder, m_Data.m_Parameters.m_BiasEnabled, biasDecoder.get(),
63 }
64 
65 } //namespace armnn
bool m_BiasEnabled
Enable/disable bias.
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
CPU Execution: Reference C++ kernels.
arm::pipe::ProfilingGuid GetGuid() const final
Definition: Workload.hpp:59
Copyright (c) 2021 ARM Limited and Contributors.
uint32_t m_DilationY
Dilation along y axis.
uint32_t m_PadTop
Padding top value in the height dimension.
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
std::vector< TensorInfo > m_InputTensorInfos
RefConvolution2dWorkload(const Convolution2dQueueDescriptor &descriptor, const WorkloadInfo &info)
void Convolve(const TensorShape &rInputShape, Decoder< float > &rInputDecoder, const TensorShape &rOutputShape, Encoder< float > &rOutputEncoder, const TensorShape &rFilterShape, Decoder< float > &rFilterDecoder, bool biasEnabled, Decoder< float > *pBiasDecoder, DataLayout dataLayout, unsigned int paddingTop, unsigned int paddingLeft, unsigned int xStride, unsigned int yStride, unsigned int xDilation, unsigned int yDilation, bool depthwise)
Definition: ConvImpl.cpp:71
std::vector< TensorInfo > m_OutputTensorInfos
uint32_t m_StrideY
Stride value when proceeding through input for the height dimension.
#define ARMNN_SCOPED_PROFILING_EVENT_GUID(backendId, name, guid)
Definition: Profiling.hpp:223
uint32_t m_DilationX
Dilation along x axis.
std::vector< ITensorHandle * > m_Outputs
#define ARMNN_REPORT_PROFILING_WORKLOAD_DESC(name, desc, infos, guid)
Definition: Profiling.hpp:227
Contains information about TensorInfos of a layer.
std::vector< ITensorHandle * > m_Inputs
void ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor) override
const TensorInfo & GetTensorInfo(const ITensorHandle *tensorHandle)
float32 helpers
uint32_t m_PadLeft
Padding left value in the width dimension.