31 static std::vector<float> Bias2({0, 2});
33 static std::vector<float> Bias4({1, 2, 3, 4});
35 static std::vector<float> Bias8({1, 2, 3, 4, 1, 2, 3, 4});
38 static std::vector<float> ConvInput3x8x16({
39 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
40 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f,
41 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
42 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
43 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
44 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
45 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
46 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
47 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
48 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
49 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
50 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
51 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
52 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
53 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
54 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
55 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
56 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
57 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
58 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
59 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
60 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
61 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
62 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
72 template<armnn::DataType ArmnnType,
typename T = armnn::ResolveType<ArmnnType>>
73 std::vector<T>
GetBias2(
bool biasEnabled,
float qScale)
77 return QuantizedVector<T>(Bias2, qScale, 0);
81 return std::vector<T>();
86 template<armnn::DataType ArmnnType,
typename T = armnn::ResolveType<ArmnnType>>
87 std::vector<T>
GetBias4(
bool biasEnabled,
float qScale)
91 return QuantizedVector<T>(Bias4, qScale, 0);
95 return std::vector<T>();
100 template<armnn::DataType ArmnnType,
typename T = armnn::ResolveType<ArmnnType>>
101 std::vector<T>
GetBias8(
bool biasEnabled,
float qScale)
105 return QuantizedVector<T>(Bias8, qScale, 0);
109 return std::vector<T>();
114 template<armnn::DataType ArmnnType,
typename T = armnn::ResolveType<ArmnnType>>
119 const unsigned int outputChannels = outputInfo.
GetShape()[channelsIndex];
121 switch (outputChannels)
126 return GetBias2<ArmnnType>(biasEnabled, qScale);
130 return GetBias4<ArmnnType>(biasEnabled, qScale);
134 return GetBias8<ArmnnType>(biasEnabled, qScale);
146 struct FullyConnectedBiasTypeForInputType;
149 struct FullyConnectedBiasTypeForInputType<float>
155 struct FullyConnectedBiasTypeForInputType<uint8_t>
157 using Type = int32_t;
161 template<
typename T,
typename B>
162 void ApplyBias(std::vector<T>& v,
float vScale, int32_t vOffset,
163 const std::vector<B>& bias,
float bScale, int32_t bOffset, uint32_t w, uint32_t h)
165 ARMNN_ASSERT_MSG((armnn::IsQuantizedType<T>() && vScale != 0.0f) || (!armnn::IsQuantizedType<T>()),
166 "Invalid type and parameter combination.");
167 ARMNN_ASSERT_MSG((armnn::IsQuantizedType<B>() && bScale != 0.0f) || (!armnn::IsQuantizedType<B>()),
168 "Invalid type and parameter combination.");
171 for (uint32_t i = 0; i < bias.size(); ++i)
174 for (uint32_t y = 0; y < h; ++y)
176 for (uint32_t x = 0; x < w; ++x)
178 uint32_t offset = (i * h + y) * w + x;
180 T& outRef = v[offset];
182 outRef = SelectiveQuantize<T>(dOutput + dBias, vScale, vOffset);
198 const std::vector<T>& originalInput,
199 const std::vector<T>& originalKernel,
200 const std::vector<B>& bias,
201 const std::vector<T>& originalOutputExpected,
208 uint32_t padLeft = 0,
210 uint32_t padRight = 0,
211 uint32_t padBottom = 0,
212 uint32_t strideX = 1,
213 uint32_t strideY = 1,
214 uint32_t dilationX = 1,
215 uint32_t dilationY = 1)
223 unsigned int outputHeight =
armnn::numeric_cast<
unsigned int>(originalOutputExpectedShape[2]);
224 unsigned int outputWidth =
armnn::numeric_cast<
unsigned int>(originalOutputExpectedShape[3]);
225 unsigned int outputChannels =
armnn::numeric_cast<
unsigned int>(originalOutputExpectedShape[1]);
226 unsigned int outputNum =
armnn::numeric_cast<
unsigned int>(originalOutputExpectedShape[0]);
233 bool biasEnabled = bias.size() > 0;
240 ARMNN_ASSERT(!biasEnabled || bias.size() == outputChannels);
249 armnn::TensorInfo biasDesc({
static_cast<unsigned int>(bias.size())}, ArmnnBType);
252 if(armnn::IsQuantizedType<T>())
254 inputTensorInfo.SetQuantizationScale(qScale);
255 inputTensorInfo.SetQuantizationOffset(qOffset);
265 std::vector<T> inputImage;
266 inputImage.assign(originalInput.data(), originalInput.data() + 1*inputChannels*inputHeight*inputWidth);
267 std::vector<T> inputData;
268 inputData.insert(inputData.end(), inputImage.begin(), inputImage.end());
269 inputData.insert(inputData.end(), inputImage.begin(), inputImage.end());
275 std::vector<T> tmp(inputData.size());
276 armnnUtils::Permute(inputTensorInfo.GetShape(), NCHWToNHWC, inputData.data(), tmp.data(),
sizeof(T));
280 std::vector<T> outputImage;
281 outputImage.assign(originalOutputExpected.data(),
282 originalOutputExpected.data() + outputChannels*outputHeight*outputWidth);
287 std::vector<T> biasV;
288 biasV.assign(bias.data(), bias.data() + outputChannels);
291 outputWidth, outputHeight);
298 std::vector<T> expectedOutput;
299 expectedOutput.insert(expectedOutput.end(), outputImage.begin(), outputImage.end());
300 expectedOutput.insert(expectedOutput.end(), outputImage.begin(), outputImage.end());
305 std::vector<T> tmp(expectedOutput.size());
307 expectedOutput = tmp;
310 std::unique_ptr<armnn::ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputTensorInfo);
311 std::unique_ptr<armnn::ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputTensorInfo);
312 std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(kernelDesc);
320 std::vector<T> kernel = originalKernel;
332 AddInputToWorkload(data, info, inputTensorInfo, inputHandle.get());
333 AddInputToWorkload(data, info, kernelDesc, weightsHandle.get());
334 AddOutputToWorkload(data, info, outputTensorInfo, outputHandle.get());
336 std::unique_ptr<armnn::ITensorHandle> biasHandle =
nullptr;
340 AddInputToWorkload(data, info, biasDesc, biasHandle.get());
343 data.
m_Bias = &biasTensor;
358 inputHandle->Allocate();
359 outputHandle->Allocate();
360 weightsHandle->Allocate();
364 biasHandle->Allocate();
371 ExecuteWorkload(*workload, memoryManager);
377 outputHandle->GetShape(),
388 const std::vector<T>& input,
389 const std::vector<T>& kernel,
390 const std::vector<B>& bias,
391 const std::vector<O>& outputExpected,
398 uint32_t padLeft = 1,
400 uint32_t padRight = 1,
401 uint32_t padBottom = 1,
402 uint32_t strideX = 1,
403 uint32_t strideY = 1)
421 bool biasEnabled = bias.size() > 0;
424 armnn::TensorInfo inputTensorInfo({inputNum, inputHeight, inputWidth, inputChannels}, ArmnnType);
425 armnn::TensorInfo outputTensorInfo({outputNum, outputHeight, outputWidth, outputChannels},
427 armnn::TensorInfo kernelDesc({kernelChanMul, kernelHeight, kernelWidth, kernelChannels}, ArmnnType);
428 armnn::TensorInfo biasDesc({
static_cast<unsigned int>(bias.size())}, ArmnnBType);
431 std::vector<T> inputData;
432 inputData.assign(input.data(), input.data() + inputHeight*inputWidth*inputChannels);
435 std::vector<O> outputData;
436 outputData.assign(outputExpected.data(), outputExpected.data() + outputHeight*outputWidth*outputChannels);
438 std::vector<O> actualOutput(outputTensorInfo.GetNumElements());
440 std::unique_ptr<armnn::ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputTensorInfo);
441 std::unique_ptr<armnn::ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputTensorInfo);
442 std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(kernelDesc);
443 std::unique_ptr<armnn::ITensorHandle> biasHandle =
nullptr;
453 data.
m_Bias = &biasTensor;
464 AddInputToWorkload(data, info, inputTensorInfo, inputHandle.get());
465 AddInputToWorkload(data, info, kernelDesc, weightsHandle.get());
466 AddOutputToWorkload(data, info, outputTensorInfo, outputHandle.get());
471 AddInputToWorkload(data, info, biasDesc, biasHandle.get());
477 inputHandle->Allocate();
478 outputHandle->Allocate();
479 weightsHandle->Allocate();
483 biasHandle->Allocate();
490 ExecuteWorkload(*workload, memoryManager);
496 outputHandle->GetShape(),
497 outputTensorInfo.GetShape());
500 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T = armnn::ResolveType<ArmnnType>>
515 unsigned int batchSize = 1;
516 unsigned int inputChannels = 2;
517 unsigned int outputChannels = 3;
518 unsigned int inputSize = 5;
519 unsigned int kernelSize = 3;
520 unsigned int padSize = 2;
521 unsigned int stride = 1;
522 unsigned int outputSize = 7;
524 armnn::TensorInfo inputInfo({batchSize, inputChannels, inputSize, 1}, ArmnnType);
525 armnn::TensorInfo outputInfo({batchSize, outputChannels, outputSize, 1}, ArmnnType);
526 armnn::TensorInfo kernelInfo({outputChannels, inputChannels, kernelSize, 1}, ArmnnType);
530 if(armnn::IsQuantizedType<T>())
533 inputInfo.SetQuantizationOffset(qOffset);
534 outputInfo.SetQuantizationScale(qScale);
535 outputInfo.SetQuantizationOffset(qOffset);
536 kernelInfo.SetQuantizationScale(qScale);
537 kernelInfo.SetQuantizationOffset(qOffset);
538 biasInfo.SetQuantizationScale(inputInfo.GetQuantizationScale()*kernelInfo.GetQuantizationScale());
539 biasInfo.SetQuantizationOffset(0);
542 std::vector<T> inputData = QuantizedVector<T>(
544 5.0f, -2.0f, 2.5f, 0.0f, 1.0f,
545 -3.0f, 3.2f, 5.0f, 2.0f, 3.0f,
547 inputInfo.GetQuantizationScale(),
548 inputInfo.GetQuantizationOffset());
550 std::vector<T> kernelData = QuantizedVector<T>(
561 kernelInfo.GetQuantizationScale(),
562 kernelInfo.GetQuantizationOffset());
564 std::vector<B> biasData =
565 QuantizedVector<B>({ 1.0f, 0.0f, 0.0f }, biasInfo.GetQuantizationScale(), biasInfo.GetQuantizationOffset());
567 std::vector<T> outputData = QuantizedVector<T>(
569 4.5f, -10.8f, 5.0f + 6.4f - 7.5f, -2.0f + 10.0f -3.0f, 2.5f + 4.0f - 4.5f, 6.0f, 1.0f,
570 -0.6f, -0.6f + 0.64f, -0.6f + 0.64f + 1.0f, 0.64f + 1.0f + 0.4f, 1.0f + 0.4f + 0.6f, 0.4f + 0.6f, 0.6f,
571 2.5f, -1.0f + 3.0f, 1.25f - 3.2f + 2.5f, -1.0f - 5.0f, 1.25f + 0.5f - 2.0f, -3.0f, 0.5f
573 outputInfo.GetQuantizationScale(),
574 outputInfo.GetQuantizationOffset());
576 std::vector<T> actualOutput(outputInfo.GetNumElements());
581 ApplyBias(outputData, outputInfo.GetQuantizationScale(), outputInfo.GetQuantizationOffset(),
582 biasData, biasInfo.GetQuantizationScale(), biasInfo.GetQuantizationOffset(),
586 std::unique_ptr<armnn::ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputInfo);
587 std::unique_ptr<armnn::ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputInfo);
588 std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(kernelInfo);
589 std::unique_ptr<armnn::ITensorHandle> biasHandle =
nullptr;
599 AddInputToWorkload(data, info, inputInfo, inputHandle.get());
600 AddInputToWorkload(data, info, kernelInfo, weightsHandle.get());
601 AddOutputToWorkload(data, info, outputInfo, outputHandle.get());
604 data.
m_Bias = &biasTensor;
616 AddInputToWorkload(data, info, biasInfo, biasHandle.get());
622 inputHandle->Allocate();
623 outputHandle->Allocate();
624 weightsHandle->Allocate();
628 biasHandle->Allocate();
635 ExecuteWorkload(*workload, memoryManager);
641 outputHandle->GetShape(),
642 outputInfo.GetShape());
645 template<armnn::DataType ArmnnType,
typename T = armnn::ResolveType<ArmnnType>>
659 std::vector<T> input =
668 std::vector<T> kernel =
677 const std::vector<float> outputData =
684 return SimpleConvolution2dNhwcTestImpl<ArmnnType, ArmnnType>(
692 inputDesc.GetShape(),
693 kernelDesc.GetShape(),
694 outputDesc.GetShape(),
700 template<armnn::DataType ArmnnType,
typename T = armnn::ResolveType<ArmnnType>>
714 std::vector<T> input =
725 std::vector<T> kernel =
734 std::vector<T> outputData =
741 uint32_t padLeft = 1;
743 uint32_t padRight = 1;
744 uint32_t padBottom = 1;
745 uint32_t strideX = 2;
746 uint32_t strideY = 2;
748 return SimpleConvolution2dNhwcTestImpl<ArmnnType, ArmnnType>(
756 inputDesc.GetShape(),
757 kernelDesc.GetShape(),
758 outputDesc.GetShape(),
770 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T = armnn::ResolveType<ArmnnType>>
782 std::vector<T> input = QuantizedVector<T>(ConvInput3x8x16, qScale, qOffset);
786 std::vector<T> kernel = QuantizedVector<T>({
828 std::vector<T> expectedOutput = QuantizedVector<T>({
829 -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24,
830 -25, -25, -25, -25, -25, -25, -25, -25, -25, -25, -25, -25, -25, -25,
831 -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f,
832 -23.5f, -23.5f, -23.5f,
833 -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f, -23.5f,
834 -23.5f, -23.5f, -23.5f,
836 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
837 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
838 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
839 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
843 return SimpleConvolution2dTestImpl<ArmnnType, ArmnnBType>(
849 GetBias2<ArmnnBType>(biasEnabled, qScale * qScale),
851 inputDesc.GetShape(),
852 kernelDesc.GetShape(),
853 outputDesc.GetShape(),
874 std::vector<unsigned int> inputShape = { 1, 3, 8, 16 };
875 std::vector<T> input = QuantizedVector<T>(ConvInput3x8x16, qScale, qOffset);
879 std::vector<T> kernel = QuantizedVector<T>({
909 std::vector<T> expectedOutput = QuantizedVector<T>({
910 -15, -15, -15, -15, -15, -15, -15, -15, -15, -15, -15, -15, -15, -15,
911 -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16,
912 -14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,
913 -14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,
914 -14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,
915 -14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,-14.5f,
917 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
918 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
919 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
920 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
921 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
922 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
926 return SimpleConvolution2dTestImpl<ArmnnType, ArmnnBType>(
932 GetBias2<ArmnnBType>(biasEnabled, qScale * qScale),
934 inputDesc.GetShape(),
935 kernelDesc.GetShape(),
936 outputDesc.GetShape(),
954 std::vector<T> input =
964 std::vector<T> kernel =
981 std::vector<T> expectedOutput =
984 -242, -594, -934, -372, 0, 0,
985 -495, -1190, -1850, -725, 0, 0,
986 -538, -1256, -1916, -748, 0, 0,
987 -273, -626, -946, -363, 0, 0,
994 return SimpleConvolution2dTestImpl<ArmnnType, ArmnnBType>(
1000 GetBias2<ArmnnBType>(
false, qScale * qScale),
1002 inputDesc.GetShape(),
1003 kernelDesc.GetShape(),
1004 outputDesc.GetShape(),
1026 std::vector<T> input =
1027 QuantizedVector<T>({
1033 }, qScale, qOffset);
1037 std::vector<T> kernel =
1038 QuantizedVector<T>({
1048 std::vector<T> expectedOutput =
1049 QuantizedVector<T>({
1050 -7140, -10580, -13940, -9300, -5230,
1051 -9590, -14120, -18520, -12290, -6860,
1052 -9980, -14560, -18960, -12560, -7000,
1053 -7518, -10904, -14144, -9318, -5152,
1054 -5032, -7256, -9376, -6142, -3368,
1058 return SimpleConvolution2dTestImpl<ArmnnType, ArmnnBType>(
1061 tensorHandleFactory,
1064 GetBias2<ArmnnBType>(
false, qScale * qScale),
1066 inputDesc.GetShape(),
1067 kernelDesc.GetShape(),
1068 outputDesc.GetShape(),
1078 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T = armnn::ResolveType<ArmnnType>>
1083 const std::vector<float>& inputNoQuantizedValues,
1085 const std::vector<float>& kernelNoQuantizedValues,
1087 const std::vector<float>& outputExpectedNoQuantizedValues,
1092 uint32_t padLeft = 0,
1093 uint32_t padTop = 0,
1094 uint32_t padRight = 0,
1095 uint32_t padBottom = 0,
1096 uint32_t strideX = 1,
1097 uint32_t strideY = 1,
1098 bool biasEnabled =
false 1134 auto input = QuantizedVector<T>(inputNoQuantizedValues,
1137 auto kernel = QuantizedVector<T>(kernelNoQuantizedValues,
1140 auto expectedOutput = QuantizedVector<T>(outputExpectedNoQuantizedValues,
1144 return SimpleConvolution2dTestImpl<ArmnnType, ArmnnBType>(
1147 tensorHandleFactory,
1150 GetBias2<ArmnnBType>(biasEnabled, qScale * qScale),
1168 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T>
1177 std::vector<float> inputNoQuantizedValues =
1179 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1180 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1181 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1182 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1183 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1184 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1185 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1186 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1187 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1188 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1192 std::vector<float> kernelNoQuantizedValues =
1202 std::vector<float> outputExpectedNoQuantizedValues =
1210 return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1213 tensorHandleFactory,
1214 inputNoQuantizedValues,
1216 kernelNoQuantizedValues,
1218 outputExpectedNoQuantizedValues,
1226 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T>
1235 std::vector<float> inputNoQuantizedValues =
1237 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1240 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1241 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1242 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1248 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1250 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1251 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1252 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1253 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1254 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1255 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1261 std::vector<float> kernelNoQuantizedValues =
1275 std::vector<float> outputExpectedNoQuantizedValues =
1283 return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1286 tensorHandleFactory,
1287 inputNoQuantizedValues,
1289 kernelNoQuantizedValues,
1291 outputExpectedNoQuantizedValues,
1299 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T>
1308 std::vector<float> inputNoQuantizedValues =
1310 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1311 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1312 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1313 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1314 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1315 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1316 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1317 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1318 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1319 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
1323 std::vector<float> kernelNoQuantizedValues =
1333 std::vector<float> outputExpectedNoQuantizedValues =
1340 uint32_t padLeft = 1;
1341 uint32_t padTop = 1;
1342 uint32_t padRight = 1;
1343 uint32_t padBottom = 1;
1345 return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1348 tensorHandleFactory,
1349 inputNoQuantizedValues,
1351 kernelNoQuantizedValues,
1353 outputExpectedNoQuantizedValues,
1368 template<armnn::DataType ArmnnType,
typename T = armnn::ResolveType<ArmnnType>>
1376 unsigned int inputHeight = 8;
1377 unsigned int inputWidth = 16;
1378 unsigned int inputChannels = 3;
1379 unsigned int inputNum = 5;
1381 unsigned int kernelHeight = 3;
1382 unsigned int kernelWidth = 3;
1384 unsigned int strideX = 2;
1385 unsigned int strideY = 3;
1386 unsigned int padX = 1;
1387 unsigned int padY = 1;
1389 unsigned int outputNum = inputNum;
1390 unsigned int outputChannels = 2;
1391 unsigned int outputHeight = (inputHeight + 2 * padY - kernelHeight + strideY) / strideY;
1392 unsigned int outputWidth = (inputWidth + 2 * padX - kernelWidth + strideX) / strideX;
1399 unsigned int inputShape[] = {inputNum, inputChannels, inputHeight, inputWidth};
1400 unsigned int outputShape[] = {outputNum, outputChannels, outputHeight, outputWidth};
1401 unsigned int kernelShape[] = {outputChannels, inputChannels, kernelHeight, kernelWidth};
1402 unsigned int biasShape[] = {outputChannels};
1409 auto input = MakeRandomTensor<T>(inputTensorInfo, 124908);
1410 auto kernel = MakeRandomTensor<T>(kernelDesc, 891234);
1411 auto bias = MakeRandomTensor<T>(biasDesc, 1028);
1414 std::vector<T> expectedOutput(outputTensorInfo.
GetNumElements());
1416 std::unique_ptr<armnn::ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputTensorInfo);
1417 std::unique_ptr<armnn::ITensorHandle> biasHandle = tensorHandleFactory.
CreateTensorHandle(biasDesc);
1418 std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(kernelDesc);
1419 std::unique_ptr<armnn::ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputTensorInfo);
1427 AddInputToWorkload(data, info, inputTensorInfo, inputHandle.get());
1428 AddInputToWorkload(data, info, kernelDesc, weightsHandle.get());
1429 AddInputToWorkload(data, info, biasDesc, biasHandle.get());
1430 AddOutputToWorkload(data, info, outputTensorInfo, outputHandle.get());
1442 data.
m_Bias = &biasTensor;
1451 std::unique_ptr<armnn::ITensorHandle> outputHandleRef = refTensorHandleFactory.
CreateTensorHandle(outputTensorInfo);
1452 std::unique_ptr<armnn::ITensorHandle> weightsHandleRef = refTensorHandleFactory.
CreateTensorHandle(kernelDesc);
1453 std::unique_ptr<armnn::ITensorHandle> biasHandleRef = refTensorHandleFactory.
CreateTensorHandle(biasDesc);
1454 std::unique_ptr<armnn::ITensorHandle> inputHandleRef = refTensorHandleFactory.
CreateTensorHandle(inputTensorInfo);
1458 SetWorkloadInput(refData, refInfo, 0, inputTensorInfo, inputHandleRef.get());
1459 SetWorkloadInput(refData, refInfo, 1, kernelDesc, weightsHandleRef.get());
1460 SetWorkloadInput(refData, refInfo, 2, biasDesc, biasHandleRef.get());
1461 SetWorkloadOutput(refData, refInfo, 0, outputTensorInfo, outputHandleRef.get());
1463 std::unique_ptr<armnn::IWorkload> workload
1465 std::unique_ptr<armnn::IWorkload> workloadRef
1468 outputHandleRef->Allocate();
1469 inputHandleRef->Allocate();
1470 weightsHandleRef->Allocate();
1471 biasHandleRef->Allocate();
1473 inputHandle->Allocate();
1474 outputHandle->Allocate();
1481 ExecuteWorkload(*workload, memoryManager);
1483 workloadRef->PostAllocationConfigure();
1484 workloadRef->Execute();
1491 outputHandle->GetShape(),
1508 std::vector<armnn::BFloat16> inputValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1541 std::vector<armnn::BFloat16> kernelValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1559 const std::vector<float> outputData =
1572 uint32_t padLeft = 1;
1573 uint32_t padTop = 1;
1574 uint32_t padRight = 1;
1575 uint32_t padBottom = 1;
1576 uint32_t strideX = 2;
1577 uint32_t strideY = 2;
1583 tensorHandleFactory,
1586 std::vector<float>(),
1588 inputDesc.GetShape(),
1589 kernelDesc.GetShape(),
1590 outputDesc.GetShape(),
1615 std::vector<armnn::BFloat16> inputValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1648 std::vector<armnn::BFloat16> kernelValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1666 const std::vector<float> outputData =
1679 uint32_t padLeft = 1;
1680 uint32_t padTop = 1;
1681 uint32_t padRight = 1;
1682 uint32_t padBottom = 1;
1683 uint32_t strideX = 2;
1684 uint32_t strideY = 2;
1690 tensorHandleFactory,
1693 std::vector<float>(),
1695 inputDesc.GetShape(),
1696 kernelDesc.GetShape(),
1697 outputDesc.GetShape(),
1719 const std::vector<T>& input,
1720 const std::vector<T>& kernel,
1721 const std::vector<B>& bias,
1722 const std::vector<T>& outputExpected,
1729 uint32_t padLeft = 0,
1730 uint32_t padTop = 0,
1731 uint32_t padRight = 0,
1732 uint32_t padBottom = 0,
1733 uint32_t strideX = 1,
1734 uint32_t strideY = 1)
1749 bool biasEnabled = bias.size() > 0;
1750 ARMNN_ASSERT(!biasEnabled || bias.size() == outputChannels);
1757 armnn::TensorInfo kernelDesc({1, kernelHeight, kernelWidth, kernelChannels}, ArmnnType);
1758 armnn::TensorInfo biasDesc({
static_cast<unsigned int>(bias.size())}, ArmnnBType);
1761 if (armnn::IsQuantizedType<T>())
1763 inputTensorInfo.SetQuantizationScale(qScale);
1764 inputTensorInfo.SetQuantizationOffset(qOffset);
1767 kernelDesc.SetQuantizationScale(qScale);
1768 kernelDesc.SetQuantizationOffset(qOffset);
1769 biasDesc.SetQuantizationScale(qScale*qScale);
1770 biasDesc.SetQuantizationOffset(0);
1774 std::vector<T> inputData;
1775 inputData.assign(input.data(), input.data() + inputChannels*inputHeight*inputWidth);
1781 std::vector<T> tmp(inputData.size());
1782 armnnUtils::Permute(inputTensorInfo.GetShape(), NCHWToNHWC, inputData.data(), tmp.data(),
sizeof(T));
1786 std::vector<T> kernelData;
1787 kernelData.assign(kernel.data(), kernel.data() + kernelHeight * kernelWidth * outputChannels);
1793 std::vector<T> tmp(kernelData.size());
1795 armnnUtils::Permute(kernelDesc.GetShape(), {0, 2, 3, 1}, kernelData.data(), tmp.data(),
sizeof(T));
1801 std::vector<T> outputData;
1802 outputData.assign(outputExpected.data(), outputExpected.data() + outputChannels*outputHeight*outputWidth);
1805 std::vector<T> biasV;
1806 biasV.assign(bias.data(), bias.data() + outputChannels);
1808 biasV, biasDesc.GetQuantizationScale(), biasDesc.GetQuantizationOffset(),
1809 outputWidth, outputHeight);
1817 std::vector<T> tmp(outputData.size());
1822 std::unique_ptr<armnn::ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputTensorInfo);
1823 std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(kernelDesc);
1824 std::unique_ptr<armnn::ITensorHandle> biasHandle =
nullptr;
1825 std::unique_ptr<armnn::ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputTensorInfo);
1841 AddInputToWorkload(data, info, inputTensorInfo, inputHandle.get());
1842 AddInputToWorkload(data, info, kernelDesc, weightsHandle.get());
1843 AddOutputToWorkload(data, info, outputTensorInfo, outputHandle.get());
1852 AddInputToWorkload(data, info, biasDesc, biasHandle.get());
1856 data.
m_Bias = &biasTensor;
1866 std::unique_ptr<armnn::IWorkload> workload
1869 inputHandle->Allocate();
1870 outputHandle->Allocate();
1874 ExecuteWorkload(*workload, memoryManager);
1880 outputHandle->GetShape(),
1884 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T = armnn::ResolveType<ArmnnType>>
1896 unsigned int inputHeight = 3;
1897 unsigned int inputWidth = 3;
1898 unsigned int inputChannels = 2;
1899 unsigned int inputNum = 1;
1901 unsigned int kernelHeight = 3;
1902 unsigned int kernelWidth = 3;
1904 unsigned int outputHeight = 1;
1905 unsigned int outputWidth = 1;
1906 unsigned int outputChannels = inputChannels;
1907 unsigned int outputNum = inputNum;
1918 if(armnn::IsQuantizedType<T>())
1924 kernelDesc.SetQuantizationScale(qScale);
1925 kernelDesc.SetQuantizationOffset(qOffset);
1926 biasDesc.SetQuantizationScale(qScale*qScale);
1927 biasDesc.SetQuantizationOffset(0);
1929 std::vector<T> inputData = std::vector<T>(
1930 QuantizedVector<T>({
1946 std::vector<T> tmp(inputData.size());
1951 std::vector<B> biasV(QuantizedVector<B>({ 0, 2 },
1952 biasDesc.GetQuantizationScale(),
1953 biasDesc.GetQuantizationOffset()));
1955 std::vector<T> kernelData = std::vector<T>(
1956 QuantizedVector<T>({
1965 kernelDesc.GetQuantizationScale(),
1966 kernelDesc.GetQuantizationOffset()));
1973 std::vector<T> tmp(kernelData.size());
1975 armnnUtils::Permute(kernelDesc.GetShape(), {0, 2, 3, 1}, kernelData.data(), tmp.data(),
sizeof(T));
1981 std::vector<T> outputImage(
1982 QuantizedVector<T>({ 0.f, 0.f },
1991 biasV, biasDesc.GetQuantizationScale(), biasDesc.GetQuantizationOffset(),
1992 outputWidth, outputHeight);
1997 std::vector<T> tmp(outputImage.size());
2004 std::unique_ptr<armnn::ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputTensorInfo);
2005 std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(kernelDesc);
2006 std::unique_ptr<armnn::ITensorHandle> biasHandle =
nullptr;
2007 std::unique_ptr<armnn::ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputTensorInfo);
2020 AddInputToWorkload(data, info, inputTensorInfo, inputHandle.get());
2021 AddInputToWorkload(data, info, kernelDesc, weightsHandle.get());
2022 AddOutputToWorkload(data, info, outputTensorInfo, outputHandle.get());
2031 AddInputToWorkload(data, info, biasDesc, biasHandle.get());
2035 data.
m_Bias = &biasTensor;
2045 std::unique_ptr<armnn::IWorkload> workload
2048 inputHandle->Allocate();
2049 outputHandle->Allocate();
2053 ExecuteWorkload(*workload, memoryManager);
2059 outputHandle->GetShape(),
2063 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T = armnn::ResolveType<ArmnnType>>
2075 unsigned int depthMultiplier = 2;
2077 unsigned int inputHeight = 8;
2078 unsigned int inputWidth = 16;
2079 unsigned int inputChannels = 2;
2080 unsigned int inputBatchSize = 1;
2082 unsigned int kernelHeight = 5;
2083 unsigned int kernelWidth = 3;
2085 unsigned int outputHeight = inputHeight - kernelHeight + 1 + 2;
2086 unsigned int outputWidth = (inputWidth - kernelWidth + 1)/2;
2087 unsigned int outputChannels = inputChannels * depthMultiplier;
2088 unsigned int outputBatchSize = inputBatchSize;
2091 inputBatchSize, inputChannels, inputHeight, inputWidth, layout, ArmnnType);
2093 outputBatchSize, outputChannels, outputHeight, outputWidth, layout, ArmnnType);
2099 if(armnn::IsQuantizedType<T>())
2105 kernelDesc.SetQuantizationScale(qScale);
2106 kernelDesc.SetQuantizationOffset(qOffset);
2107 biasDesc.SetQuantizationScale(qScale*qScale);
2108 biasDesc.SetQuantizationOffset(0);
2112 std::vector<T> originalInputData = std::vector<T>(
2113 QuantizedVector<T>({
2114 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
2115 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f,
2116 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
2117 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
2118 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
2119 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
2120 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
2121 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f, 0.5f,
2122 0.0f, 0.0f, 1.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f,
2123 0.0f, 0.0f, 1.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f,
2124 0.0f, 0.0f, 1.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f,
2125 0.0f, 0.0f, 1.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f,
2126 0.0f, 0.0f, 1.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f,
2127 0.0f, 0.0f, 1.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f,
2128 0.0f, 0.0f, 1.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f,
2129 0.0f, 0.0f, 1.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f
2134 std::vector<T> inputData = originalInputData;
2140 originalInputData.data(), inputData.data(),
sizeof(T));
2143 std::vector<B> biasV = QuantizedVector<B>({ 0, 2, 1, -1 },
2144 biasDesc.GetQuantizationScale(),
2145 biasDesc.GetQuantizationOffset());
2147 std::vector<T> kernelData = std::vector<T>(
2148 QuantizedVector<T>({
2173 kernelDesc.GetQuantizationScale(),
2174 kernelDesc.GetQuantizationOffset()));
2181 std::vector<T> tmp(kernelData.size());
2183 armnnUtils::Permute(kernelDesc.GetShape(), {0, 2, 3, 1}, kernelData.data(), tmp.data(),
sizeof(T));
2189 std::vector<T> originalOutputImage = std::vector<T>(
2190 QuantizedVector<T>({
2191 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2192 5, 5, 5, 5, 5, 5, 5, 5.5, 5.5, 5.5, 5.5, 5.5, 5.5, 5.5,
2193 5.5, 5.5, 5.5, 5.5, 5.5, 5.5, 5.5, 5, 5, 5, 5, 5, 5, 5,
2194 2.5, 2.5, 2.5, 2.5, 2.5, 2.5, 2.5, 3.5, 3.5, 3.5, 3.5, 3.5, 3.5, 3.5,
2195 4.5, 4.5, 4.5, 4.5, 4.5, 4.5, 4.5, 6, 6, 6, 6, 6, 6, 6,
2196 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
2197 1, 3, 0, 0, 0, 0, 0, 2, 4, 0, 0, 0, 0, 0,
2198 2, 4, 0, 0, 0, 0, 0, 2, 4, 0, 0, 0, 0, 0,
2199 2, 4, 0, 0, 0, 0, 0, 2, 4, 0, 0, 0, 0, 0,
2200 2, 4, 0, 0, 0, 0, 0, 3, 5, 0, 0, 0, 0, 0,
2201 3, 5, 0, 0, 0, 0, 0, 3, 5, 0, 0, 0, 0, 0,
2202 3, 5, 0, 0, 0, 0, 0, 3, 5, 0, 0, 0, 0, 0
2214 biasDesc.GetQuantizationScale(),
2215 biasDesc.GetQuantizationOffset(),
2220 std::vector<T> outputImage = originalOutputImage;
2224 originalOutputImage.data(), outputImage.data(),
sizeof(T));
2229 std::unique_ptr<armnn::ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputTensorInfo);
2230 std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(kernelDesc);
2231 std::unique_ptr<armnn::ITensorHandle> biasHandle =
nullptr;
2232 std::unique_ptr<armnn::ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputTensorInfo);
2245 AddInputToWorkload(data, info, inputTensorInfo, inputHandle.get());
2246 AddInputToWorkload(data, info, kernelDesc, weightsHandle.get());
2247 AddOutputToWorkload(data, info, outputTensorInfo, outputHandle.get());
2256 AddInputToWorkload(data, info, biasDesc, biasHandle.get());
2260 data.
m_Bias = &biasTensor;
2270 std::unique_ptr<armnn::IWorkload> workload
2273 inputHandle->Allocate();
2274 outputHandle->Allocate();
2278 ExecuteWorkload(*workload, memoryManager);
2284 outputHandle->GetShape(),
2295 const std::vector<T>& originalInput,
2296 const std::vector<T>& originalKernel,
2297 const std::vector<B>& bias,
2298 const std::vector<T>& originalOutputExpected,
2305 uint32_t padLeft = 0,
2306 uint32_t padTop = 0,
2307 uint32_t padRight = 0,
2308 uint32_t padBottom = 0,
2309 uint32_t strideX = 1,
2310 uint32_t strideY = 1,
2311 uint32_t dilationX = 1,
2312 uint32_t dilationY = 1)
2319 unsigned int outputHeight =
armnn::numeric_cast<
unsigned int>(originalOutputExpectedShape[2]);
2320 unsigned int outputWidth =
armnn::numeric_cast<
unsigned int>(originalOutputExpectedShape[3]);
2321 unsigned int outputChannels =
armnn::numeric_cast<
unsigned int>(originalOutputExpectedShape[1]);
2322 unsigned int outputNum =
armnn::numeric_cast<
unsigned int>(originalOutputExpectedShape[0]);
2328 bool biasEnabled = bias.size() > 0;
2335 ARMNN_ASSERT(!biasEnabled || bias.size() == outputChannels);
2345 armnn::TensorInfo kernelDesc({1, kernelHeight, kernelWidth, kernelChannels}, ArmnnType);
2347 armnn::TensorInfo biasDesc({
static_cast<unsigned int>(bias.size())}, ArmnnBType);
2350 if(armnn::IsQuantizedType<T>())
2352 inputTensorInfo.SetQuantizationScale(qScale);
2353 inputTensorInfo.SetQuantizationOffset(qOffset);
2356 kernelDesc.SetQuantizationScale(qScale);
2357 kernelDesc.SetQuantizationOffset(qOffset);
2358 biasDesc.SetQuantizationScale(qScale*qScale);
2359 biasDesc.SetQuantizationOffset(0);
2362 std::vector<T> kernelData;
2363 kernelData.assign(originalKernel.data(), originalKernel.data() + kernelHeight*kernelWidth*outputChannels);
2369 std::vector<T> tmp(kernelData.size());
2371 armnnUtils::Permute(kernelDesc.GetShape(), {0, 2, 3, 1}, kernelData.data(), tmp.data(),
sizeof(T));
2377 std::vector<T> input;
2378 input.assign(originalInput.data(), originalInput.data() + 1*inputChannels*inputHeight*inputWidth);
2379 std::vector<T> inputData;
2380 inputData.insert(inputData.end(), input.begin(), input.end());
2381 inputData.insert(inputData.end(), input.begin(), input.end());
2387 std::vector<T> tmp(inputData.size());
2388 armnnUtils::Permute(inputTensorInfo.GetShape(), NCHWToNHWC, inputData.data(), tmp.data(),
sizeof(T));
2392 std::vector<T> output;
2393 output.assign(originalOutputExpected.data(),
2394 originalOutputExpected.data() + outputChannels*outputHeight*outputWidth);
2399 std::vector<T> biasV;
2400 biasV.assign(bias.data(), bias.data() + outputChannels);
2402 biasV, biasDesc.GetQuantizationScale(), biasDesc.GetQuantizationOffset(),
2403 outputWidth, outputHeight);
2409 std::vector<T> outputData;
2410 outputData.insert(outputData.end(), output.begin(), output.end());
2411 outputData.insert(outputData.end(), output.begin(), output.end());
2416 std::vector<T> tmp(outputData.size());
2421 std::unique_ptr<armnn::ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputTensorInfo);
2422 std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(kernelDesc);
2423 std::unique_ptr<armnn::ITensorHandle> biasHandle =
nullptr;
2424 std::unique_ptr<armnn::ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputTensorInfo);
2437 AddInputToWorkload(data, info, inputTensorInfo, inputHandle.get());
2438 AddInputToWorkload(data, info, kernelDesc, weightsHandle.get());
2439 AddOutputToWorkload(data, info, outputTensorInfo, outputHandle.get());
2448 AddInputToWorkload(data, info, biasDesc, biasHandle.get());
2452 data.
m_Bias = &biasTensor;
2464 std::unique_ptr<armnn::IWorkload> workload
2467 inputHandle->Allocate();
2468 outputHandle->Allocate();
2472 ExecuteWorkload(*workload, memoryManager);
2478 outputHandle->GetShape(),
2495 auto input = QuantizedVector<T>(
2509 inputTensorInfo.GetQuantizationScale(),
2510 inputTensorInfo.GetQuantizationOffset());
2515 auto kernel = QuantizedVector<T>({
2526 kernelTensorInfo.GetQuantizationScale(),
2527 kernelTensorInfo.GetQuantizationOffset());
2532 auto expectedOutput = QuantizedVector<T>(
2534 396, 664, 820, 756, 602, 1016, 1608, 1880, 1652, 1268, 1976, 2968, 3240, 2732,
2535 2028, 2628, 3808, 4060, 3312, 2390, 2596, 3700, 3900, 3130, 2226, 2817, 4186,
2536 4330, 3609, 2651, 5414, 7864, 8120, 6626, 4780, 6314, 9144, 9400, 7646, 5500,
2537 6759, 9610, 9850, 7875, 5579, 5935, 8348, 8540, 6757, 4742
2539 outputTensorInfo.GetQuantizationScale(),
2540 outputTensorInfo.GetQuantizationOffset());
2542 return DepthwiseConvolution2dAsymmetricTestImpl<ArmnnType, ArmnnBType>(
2545 tensorHandleFactory,
2548 GetBias2<ArmnnBType>(biasEnabled, qScale * qScale),
2550 inputTensorInfo.GetShape(),
2551 kernelTensorInfo.GetShape(),
2552 outputTensorInfo.GetShape(),
2577 auto input = QuantizedVector<T>(
2591 inputTensorInfo.GetQuantizationScale(),
2592 inputTensorInfo.GetQuantizationOffset());
2595 auto kernel = QuantizedVector<T>({
2606 kernelTensorInfo.GetQuantizationScale(),
2607 kernelTensorInfo.GetQuantizationOffset());
2610 auto expectedOutput = QuantizedVector<T>(
2612 396,664,820,756,602,
2613 1016,1608,1880,1652,1268,
2614 1976,2968,3240,2732,2028,
2615 2628,3808,4060,3312,2390,
2616 2596,3700,3900,3130,2226,
2618 2817,4186,4330,3609,2651,
2619 5414,7864,8120,6626,4780,
2620 6314,9144,9400,7646,5500,
2621 6759,9610,9850,7875,5579,
2622 5935,8348,8540,6757,4742
2624 outputTensorInfo.GetQuantizationScale(),
2625 outputTensorInfo.GetQuantizationOffset());
2627 return DepthwiseConvolution2dTestImpl<ArmnnType, ArmnnBType>(
2630 tensorHandleFactory,
2633 GetBias2<ArmnnBType>(biasEnabled, qScale * qScale),
2635 inputTensorInfo.GetShape(),
2636 kernelTensorInfo.GetShape(),
2637 outputTensorInfo.GetShape(),
2662 auto input = QuantizedVector<T>(
2664 0, 0, 0, 0, 0, 0, 0, 0, 0,
2665 0, 0, 0, 0, 0, 0, 0, 0, 0,
2666 0, 0, 0, 0, 0, 0, 0, 0, 0,
2667 0, 0, 0, 1, 1, 1, 0, 0, 0,
2668 0, 0, 0, 1, 1, 1, 0, 0, 0,
2669 0, 0, 0, 1, 1, 1, 0, 0, 0,
2670 0, 0, 0, 0, 0, 0, 0, 0, 0,
2671 0, 0, 0, 0, 0, 0, 0, 0, 0,
2672 0, 0, 0, 0, 0, 0, 0, 0, 0
2674 inputTensorInfo.GetQuantizationScale(),
2675 inputTensorInfo.GetQuantizationOffset());
2678 auto kernel = QuantizedVector<T>({
2683 kernelTensorInfo.GetQuantizationScale(),
2684 kernelTensorInfo.GetQuantizationOffset());
2686 uint32_t padLeft = 0;
2687 uint32_t padTop = 0;
2688 uint32_t padRight = 0;
2689 uint32_t padBottom = 0;
2690 uint32_t strideX = 1;
2691 uint32_t strideY = 1;
2692 uint32_t dilationX = 3;
2693 uint32_t dilationY = 3;
2697 auto expectedOutput = QuantizedVector<T>(
2703 outputTensorInfo.GetQuantizationScale(),
2704 outputTensorInfo.GetQuantizationOffset());
2706 return DepthwiseConvolution2dTestImpl<ArmnnType, ArmnnBType>(
2709 tensorHandleFactory,
2712 GetBias2<ArmnnBType>(biasEnabled, qScale * qScale),
2714 inputTensorInfo.GetShape(),
2715 kernelTensorInfo.GetShape(),
2716 outputTensorInfo.GetShape(),
2730 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T = armnn::ResolveType<ArmnnType>>
2735 const std::vector<float>& inputNoQuantizedValues,
2737 const std::vector<float>& kernelNoQuantizedValues,
2739 const std::vector<float>& outputExpectedNoQuantizedValues,
2744 bool biasEnabled =
false)
2779 auto input = QuantizedVector<T>(inputNoQuantizedValues,
2782 auto kernel = QuantizedVector<T>(kernelNoQuantizedValues,
2785 auto expectedOutput = QuantizedVector<T>(outputExpectedNoQuantizedValues,
2789 uint32_t padLeft = 0;
2790 uint32_t padTop = 0;
2791 uint32_t padRight = 0;
2792 uint32_t padBottom = 0;
2793 uint32_t strideX = 1;
2794 uint32_t strideY = 1;
2796 return DepthwiseConvolution2dTestImpl<ArmnnType, ArmnnBType>(
2799 tensorHandleFactory,
2802 GetBias<ArmnnBType>(biasEnabled, qScale * qScale, outputTensorInfo, layout),
2806 outputTensorInfo.GetShape(),
2820 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T>
2829 std::vector<float> inputNoQuantizedValues =
2831 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2832 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2833 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2834 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2835 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2836 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2837 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2838 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2839 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2840 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2844 std::vector<float> kernelNoQuantizedValues =
2854 std::vector<float> outputExpectedNoQuantizedValues =
2862 return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2865 tensorHandleFactory,
2866 inputNoQuantizedValues,
2868 kernelNoQuantizedValues,
2870 outputExpectedNoQuantizedValues,
2878 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T>
2887 std::vector<float> inputNoQuantizedValues =
2889 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2890 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2891 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2892 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2893 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2894 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2895 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2896 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2897 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2898 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2900 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2901 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2902 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2903 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2904 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2905 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2906 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2907 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2908 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2909 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2913 std::vector<float> kernelNoQuantizedValues =
2927 std::vector<float> outputExpectedNoQuantizedValues =
2929 2, 9, 9, 9, 2, 9, 9, 9, 2, 9, 9, 9, 5, 3, 3, 3, 3,
2931 1, 1, 1, 3, 1, 1, 1, 3, 1, 1, 1, 6, 4, 4, 4
2934 return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2937 tensorHandleFactory,
2938 inputNoQuantizedValues,
2940 kernelNoQuantizedValues,
2942 outputExpectedNoQuantizedValues,
2950 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T>
2959 std::vector<float> inputNoQuantizedValues =
2972 std::vector<float> kernelNoQuantizedValues =
3000 std::vector<float> outputExpectedNoQuantizedValues =
3002 4.5f, 4.5f, 4.5f, 4.5f, 5.5f, 5.5f, 5.5f, 5.5f,
3003 2.5f, 2.5f, 2.5f, 2.5f, 3.5f, 3.5f, 3.5f, 3.5f,
3004 10.05f, 10.5f, 11.4f, 11.85f, 12.75f, 13.3f, 14.4f, 14.95f,
3005 5.25f, 5.5f, 6.0f, 6.25f, 7.45f, 7.8f, 8.5f, 8.85f
3009 return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
3012 tensorHandleFactory,
3013 inputNoQuantizedValues,
3015 kernelNoQuantizedValues,
3017 outputExpectedNoQuantizedValues,
3025 template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType,
typename T>
3034 std::vector<float> inputNoQuantizedValues =
3047 std::vector<float> kernelNoQuantizedValues =
3064 std::vector<float> outputExpectedNoQuantizedValues =
3066 4.5f, 4.5f, 4.5f, 4.5f,
3067 5.5f, 5.5f, 5.5f, 5.5f,
3068 5.25f, 5.5f, 6.0f, 6.25f,
3069 7.65f, 8.0f, 8.7f, 9.05f
3073 return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
3076 tensorHandleFactory,
3077 inputNoQuantizedValues,
3079 kernelNoQuantizedValues,
3081 outputExpectedNoQuantizedValues,
3089 template<armnn::DataType ArmnnType,
typename T = armnn::ResolveType<ArmnnType>>
3098 unsigned int inputHeight = 8;
3099 unsigned int inputWidth = 16;
3100 unsigned int inputChannels = 3;
3101 unsigned int inputNum = 5;
3103 unsigned int kernelHeight = 3;
3104 unsigned int kernelWidth = 3;
3105 unsigned int channelMultiplier = 1;
3107 unsigned int strideX = 2;
3108 unsigned int strideY = 3;
3109 unsigned int padX = 1;
3110 unsigned int padY = 1;
3112 unsigned int outputNum = inputNum;
3113 unsigned int outputChannels = inputChannels * channelMultiplier;
3114 unsigned int outputHeight = (inputHeight + 2 * padY - kernelHeight + strideY) / strideY;
3115 unsigned int outputWidth = (inputWidth + 2 * padX - kernelWidth + strideX) / strideX;
3122 std::vector<unsigned int> inputShape;
3123 std::vector<unsigned int> outputShape;
3124 std::vector<unsigned int> kernelShape{ 1, kernelHeight, kernelWidth, outputChannels };
3125 std::vector<unsigned int> biasShape{ outputChannels };
3129 inputShape = { inputNum, inputChannels, inputHeight, inputWidth };
3130 outputShape = { outputNum, outputChannels, outputHeight, outputWidth };
3133 inputShape = { inputNum, inputHeight, inputWidth, inputChannels };
3134 outputShape = { outputNum, outputHeight, outputWidth, outputChannels };
3138 + std::to_string(static_cast<int>(layout.
GetDataLayout())) +
"]");
3141 float inputsQScale = armnn::IsQuantizedType<T>() ? 1.0f : 0;
3142 float outputQScale = armnn::IsQuantizedType<T>() ? 2.0f : 0;
3143 int32_t qOffset = 0;
3145 inputTensorInfo =
armnn::TensorInfo(4, inputShape.data(), ArmnnType, inputsQScale, qOffset);
3146 outputTensorInfo =
armnn::TensorInfo(4, outputShape.data(), ArmnnType, outputQScale, qOffset);
3147 kernelDesc =
armnn::TensorInfo(4, kernelShape.data(), ArmnnType, inputsQScale, qOffset);
3150 auto input = MakeRandomTensor<T>(inputTensorInfo, 124908, 0.0f, 255.0f);
3151 auto kernel = MakeRandomTensor<T>(kernelDesc, 891234, 0.0f, 255.0f);
3152 auto bias = MakeRandomTensor<typename FullyConnectedBiasTypeForInputType<T>::Type>(biasDesc, 1028, 0.0f, 255.0f);
3155 std::vector<T> aclKernelData;
3156 aclKernelData.assign(kernel.data(), kernel.data() + kernelHeight * kernelWidth * outputChannels);
3162 std::vector<T> tmp(kernel.size());
3164 armnnUtils::Permute(kernelDesc.GetShape(), {0, 2, 3, 1}, kernel.data(), tmp.data(),
sizeof(T));
3165 aclKernelData = tmp;
3170 std::vector<T> expectedOutput(outputTensorInfo.
GetNumElements());
3172 std::unique_ptr<armnn::ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputTensorInfo);
3173 std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(aclKernelDescriptor);
3174 std::unique_ptr<armnn::ITensorHandle> biasHandle = tensorHandleFactory.
CreateTensorHandle(biasDesc);
3175 std::unique_ptr<armnn::ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputTensorInfo);
3183 AddInputToWorkload(data, info, inputTensorInfo, inputHandle.get());
3184 AddInputToWorkload(data, info, aclKernelDescriptor, weightsHandle.get());
3185 AddInputToWorkload(data, info, biasDesc, biasHandle.get());
3186 AddOutputToWorkload(data, info, outputTensorInfo, outputHandle.get());
3198 data.
m_Bias = &biasTensor;
3208 std::unique_ptr<armnn::ITensorHandle> outputHandleRef = refTensorHandleFactory.
CreateTensorHandle(outputTensorInfo);
3209 std::unique_ptr<armnn::ITensorHandle> weightsHandleRef = refTensorHandleFactory.
CreateTensorHandle(kernelDesc);
3210 std::unique_ptr<armnn::ITensorHandle> biasHandleRef = refTensorHandleFactory.
CreateTensorHandle(biasDesc);
3211 std::unique_ptr<armnn::ITensorHandle> inputHandleRef = refTensorHandleFactory.
CreateTensorHandle(inputTensorInfo);
3215 SetWorkloadInput(refData, refInfo, 0, inputTensorInfo, inputHandleRef.get());
3216 SetWorkloadInput(refData, refInfo, 1, kernelDesc, weightsHandleRef.get());
3217 SetWorkloadInput(refData, refInfo, 2, biasDesc, biasHandleRef.get());
3218 SetWorkloadOutput(refData, refInfo, 0, outputTensorInfo, outputHandleRef.get());
3220 std::unique_ptr<armnn::IWorkload> workload
3222 std::unique_ptr<armnn::IWorkload> workloadRef
3225 outputHandleRef->Allocate();
3226 weightsHandleRef->Allocate();
3227 biasHandleRef->Allocate();
3228 inputHandleRef->Allocate();
3230 inputHandle->Allocate();
3231 outputHandle->Allocate();
3238 ExecuteWorkload(*workload, memoryManager);
3240 workloadRef->PostAllocationConfigure();
3241 workloadRef->Execute();
3248 outputHandle->GetShape(),
3256 Convolution2d3x3Dilation3x3Test<armnn::DataType::BFloat16, armnn::DataType::BFloat16>(
3264 Convolution2d3x3Dilation3x3Test<armnn::DataType::Float32, armnn::DataType::Float32>(
3265 armnn::IWorkloadFactory&,
3266 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3267 const armnn::ITensorHandleFactory&,
3272 Convolution2d3x3Dilation3x3Test<armnn::DataType::QAsymmS8, armnn::DataType::Signed32>(
3273 armnn::IWorkloadFactory&,
3274 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3275 const armnn::ITensorHandleFactory&,
3280 Convolution2d3x3Dilation3x3Test<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3281 armnn::IWorkloadFactory&,
3282 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3283 const armnn::ITensorHandleFactory&,
3288 Convolution2d3x3Dilation3x3Test<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3289 armnn::IWorkloadFactory&,
3290 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3291 const armnn::ITensorHandleFactory&,
3295 template LayerTestResult<armnn::ResolveType<armnn::DataType::Float32>, 4>
3296 Convolution2d2x3x3Dilation3x3Test<armnn::DataType::Float32, armnn::DataType::Float32>(
3297 armnn::IWorkloadFactory&,
3298 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3299 const armnn::ITensorHandleFactory&,
3303 template LayerTestResult<armnn::ResolveType<armnn::DataType::BFloat16>, 4>
3304 Convolution2d2x3x3Dilation3x3Test<armnn::DataType::BFloat16, armnn::DataType::BFloat16>(
3305 armnn::IWorkloadFactory&,
3306 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3307 const armnn::ITensorHandleFactory&,
3311 template LayerTestResult<armnn::ResolveType<armnn::DataType::QAsymmS8>, 4>
3312 Convolution2d2x3x3Dilation3x3Test<armnn::DataType::QAsymmS8, armnn::DataType::Signed32>(
3313 armnn::IWorkloadFactory&,
3314 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3315 const armnn::ITensorHandleFactory&,
3319 template LayerTestResult<armnn::ResolveType<armnn::DataType::QAsymmU8>, 4>
3320 Convolution2d2x3x3Dilation3x3Test<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3321 armnn::IWorkloadFactory&,
3322 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3323 const armnn::ITensorHandleFactory&,
3327 template LayerTestResult<armnn::ResolveType<armnn::DataType::QSymmS16>, 4>
3328 Convolution2d2x3x3Dilation3x3Test<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3329 armnn::IWorkloadFactory&,
3330 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3331 const armnn::ITensorHandleFactory&,
3335 template LayerTestResult<armnn::ResolveType<armnn::DataType::BFloat16>, 4>
3336 Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test<armnn::DataType::BFloat16, armnn::DataType::BFloat16>(
3337 armnn::IWorkloadFactory &workloadFactory,
3338 const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager,
3339 const armnn::ITensorHandleFactory& tensorHandleFactory,
3343 template LayerTestResult<armnn::ResolveType<armnn::DataType::Float32>, 4>
3344 Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test<armnn::DataType::Float32, armnn::DataType::Float32>(
3345 armnn::IWorkloadFactory &workloadFactory,
3346 const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager,
3347 const armnn::ITensorHandleFactory& tensorHandleFactory,
3351 template LayerTestResult<armnn::ResolveType<armnn::DataType::QAsymmS8>, 4>
3352 Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test<armnn::DataType::QAsymmS8, armnn::DataType::Signed32>(
3353 armnn::IWorkloadFactory &workloadFactory,
3354 const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager,
3355 const armnn::ITensorHandleFactory& tensorHandleFactory,
3359 template LayerTestResult<armnn::ResolveType<armnn::DataType::QAsymmU8>, 4>
3360 Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3361 armnn::IWorkloadFactory &workloadFactory,
3362 const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager,
3363 const armnn::ITensorHandleFactory& tensorHandleFactory,
3367 template LayerTestResult<armnn::ResolveType<armnn::DataType::QSymmS16>, 4>
3368 Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3369 armnn::IWorkloadFactory &workloadFactory,
3370 const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager,
3371 const armnn::ITensorHandleFactory& tensorHandleFactory,
3375 template LayerTestResult<armnn::ResolveType<armnn::DataType::BFloat16>, 4>
3376 DepthwiseConvolution2d3x3Dilation3x3Test<armnn::DataType::BFloat16, armnn::DataType::BFloat16>(
3377 armnn::IWorkloadFactory&,
3378 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3379 const armnn::ITensorHandleFactory&,
3383 template LayerTestResult<armnn::ResolveType<armnn::DataType::Float32>, 4>
3384 DepthwiseConvolution2d3x3Dilation3x3Test<armnn::DataType::Float32, armnn::DataType::Float32>(
3385 armnn::IWorkloadFactory&,
3386 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3387 const armnn::ITensorHandleFactory&,
3391 template LayerTestResult<armnn::ResolveType<armnn::DataType::QAsymmS8>, 4>
3392 DepthwiseConvolution2d3x3Dilation3x3Test<armnn::DataType::QAsymmS8, armnn::DataType::Signed32>(
3393 armnn::IWorkloadFactory&,
3394 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3395 const armnn::ITensorHandleFactory&,
3399 template LayerTestResult<armnn::ResolveType<armnn::DataType::QAsymmU8>, 4>
3400 DepthwiseConvolution2d3x3Dilation3x3Test<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3401 armnn::IWorkloadFactory&,
3402 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3403 const armnn::ITensorHandleFactory&,
3407 template LayerTestResult<armnn::ResolveType<armnn::DataType::QSymmS16>, 4>
3408 DepthwiseConvolution2d3x3Dilation3x3Test<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3409 armnn::IWorkloadFactory&,
3410 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3411 const armnn::ITensorHandleFactory&,
3415 template LayerTestResult<armnn::ResolveType<armnn::DataType::BFloat16>, 4>
3416 DepthwiseConvolution2d2x3x3Dilation3x3Test<armnn::DataType::BFloat16, armnn::DataType::BFloat16>(
3417 armnn::IWorkloadFactory&,
3418 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3419 const armnn::ITensorHandleFactory&,
3423 template LayerTestResult<armnn::ResolveType<armnn::DataType::Float32>, 4>
3424 DepthwiseConvolution2d2x3x3Dilation3x3Test<armnn::DataType::Float32, armnn::DataType::Float32>(
3425 armnn::IWorkloadFactory&,
3426 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3427 const armnn::ITensorHandleFactory&,
3431 template LayerTestResult<armnn::ResolveType<armnn::DataType::QAsymmS8>, 4>
3432 DepthwiseConvolution2d2x3x3Dilation3x3Test<armnn::DataType::QAsymmS8, armnn::DataType::Signed32>(
3433 armnn::IWorkloadFactory&,
3434 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3435 const armnn::ITensorHandleFactory&,
3439 template LayerTestResult<armnn::ResolveType<armnn::DataType::QAsymmU8>, 4>
3440 DepthwiseConvolution2d2x3x3Dilation3x3Test<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3441 armnn::IWorkloadFactory&,
3442 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3443 const armnn::ITensorHandleFactory&,
3447 template LayerTestResult<armnn::ResolveType<armnn::DataType::QSymmS16>, 4>
3448 DepthwiseConvolution2d2x3x3Dilation3x3Test<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3449 armnn::IWorkloadFactory&,
3450 const armnn::IBackendInternal::IMemoryManagerSharedPtr&,
3451 const armnn::ITensorHandleFactory&,
3455 template LayerTestResult<armnn::ResolveType<armnn::DataType::BFloat16>, 4>
3456 DepthwiseConvolution2dMult4Test<armnn::DataType::BFloat16, armnn::DataType::BFloat16>(
3457 armnn::IWorkloadFactory &workloadFactory,
3458 const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager,
3459 const armnn::ITensorHandleFactory& tensorHandleFactory,
3463 template LayerTestResult<armnn::ResolveType<armnn::DataType::Float32>, 4>
3464 DepthwiseConvolution2dMult4Test<armnn::DataType::Float32, armnn::DataType::Float32>(
3465 armnn::IWorkloadFactory &workloadFactory,
3466 const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager,
3467 const armnn::ITensorHandleFactory& tensorHandleFactory,
3471 template LayerTestResult<armnn::ResolveType<armnn::DataType::BFloat16>, 4>
3472 DepthwiseConvolution2dMult2Test<armnn::DataType::BFloat16, armnn::DataType::BFloat16>(
3473 armnn::IWorkloadFactory &workloadFactory,
3474 const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager,
3475 const armnn::ITensorHandleFactory& tensorHandleFactory,
3479 template LayerTestResult<armnn::ResolveType<armnn::DataType::Float32>, 4>
3480 DepthwiseConvolution2dMult2Test<armnn::DataType::Float32, armnn::DataType::Float32>(
3481 armnn::IWorkloadFactory &workloadFactory,
3482 const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager,
3483 const armnn::ITensorHandleFactory& tensorHandleFactory,
3492 armnn::IWorkloadFactory& workloadFactory,
3493 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3494 const armnn::ITensorHandleFactory& tensorHandleFactory,
3498 return SimpleConvolution2d3x5TestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3499 workloadFactory, memoryManager, tensorHandleFactory, 0.f, 0, biasEnabled, layout);
3503 armnn::IWorkloadFactory& workloadFactory,
3504 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3505 const armnn::ITensorHandleFactory& tensorHandleFactory,
3509 return SimpleConvolution2d3x5TestCommon<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3510 workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3514 armnn::IWorkloadFactory& workloadFactory,
3515 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3516 const armnn::ITensorHandleFactory& tensorHandleFactory,
3520 return SimpleConvolution2d3x3TestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3521 workloadFactory, memoryManager, tensorHandleFactory, 0.f, 0, biasEnabled, layout);
3525 armnn::IWorkloadFactory& workloadFactory,
3526 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3527 const armnn::ITensorHandleFactory& tensorHandleFactory,
3530 return SimpleConvolution2d3x3NhwcTestCommon<armnn::DataType::Float32>(
3533 tensorHandleFactory,
3541 armnn::IWorkloadFactory& workloadFactory,
3542 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3543 const armnn::ITensorHandleFactory& tensorHandleFactory,
3547 return SimpleConvolution2d3x3Stride2x2TestCommon<armnn::DataType::Float32>(
3550 tensorHandleFactory,
3558 armnn::IWorkloadFactory& workloadFactory,
3559 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3560 const armnn::ITensorHandleFactory& tensorHandleFactory,
3564 return SimpleConvolution2d3x3TestCommon<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3565 workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3569 armnn::IWorkloadFactory& workloadFactory,
3570 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3571 const armnn::ITensorHandleFactory& tensorHandleFactory,
3575 return SimpleConvolution2d3x5TestCommon<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3576 workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3580 armnn::IWorkloadFactory& workloadFactory,
3581 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3582 const armnn::ITensorHandleFactory& tensorHandleFactory,
3586 return SimpleConvolution2d3x3TestCommon<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3587 workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3591 armnn::IWorkloadFactory& workloadFactory,
3592 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3593 const armnn::ITensorHandleFactory& tensorHandleFactory,
3596 return SimpleConvolution2dAsymmetricPaddingTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3597 workloadFactory, memoryManager, tensorHandleFactory, layout, 0.0f, 0);
3601 armnn::IWorkloadFactory& workloadFactory,
3602 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3603 const armnn::ITensorHandleFactory& tensorHandleFactory,
3608 workloadFactory, memoryManager, tensorHandleFactory, layout, 0.0f, 0);
3612 armnn::IWorkloadFactory& workloadFactory,
3613 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3614 const armnn::ITensorHandleFactory& tensorHandleFactory,
3617 return Convolution1dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3618 workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled);
3622 armnn::IWorkloadFactory& workloadFactory,
3623 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3624 const armnn::ITensorHandleFactory& tensorHandleFactory,
3627 return Convolution1dTestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3628 workloadFactory, memoryManager, tensorHandleFactory, 0.1f, 128, biasEnabled);
3632 armnn::IWorkloadFactory& workloadFactory,
3633 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3634 const armnn::ITensorHandleFactory& tensorHandleFactory,
3637 using namespace armnn;
3639 const DataType inputType = DataType::QAsymmU8;
3640 const DataType kernelType = DataType::QSymmS8;
3641 const DataType biasType = DataType::Signed32;
3643 TensorInfo inputInfo ({ 1, 3, 1, 2 }, inputType, 0.5f, 128);
3644 TensorInfo outputInfo({ 1, 3, 1, 3 }, inputType, 1.0f, 128);
3646 const std::vector<float> quantScales{ 0.5f, 0.75f, 1.0f };
3647 constexpr
unsigned int quantDimension = 0;
3649 TensorInfo kernelInfo({ 3, 1, 1, 2 }, kernelType, quantScales, quantDimension);
3651 const std::vector<float> biasQuantScales{ 0.25f, 0.375f, 0.5f };
3652 TensorInfo biasInfo({ 3 }, biasType, biasQuantScales, quantDimension);
3654 std::vector<uint8_t> inputData =
3656 138, 108, 138, 108, 138, 108
3659 std::vector<int8_t> kernelData =
3664 std::vector<int32_t> biasData =
3669 std::vector<uint8_t> expectedOutputData =
3671 121, 118, 115, 121, 118, 115, 121, 118, 115
3681 std::vector<uint8_t> actualOutput(outputInfo.GetNumElements());
3685 descriptor.m_StrideY = 1;
3686 descriptor.m_PadLeft = 0;
3687 descriptor.m_PadRight = 0;
3688 descriptor.m_PadTop = 0;
3689 descriptor.m_PadBottom = 0;
3690 descriptor.m_BiasEnabled =
true;
3691 descriptor.m_DataLayout = layout;
3693 std::unique_ptr<ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputInfo);
3694 std::unique_ptr<ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputInfo);
3695 std::unique_ptr<armnn::ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(kernelInfo);
3696 std::unique_ptr<armnn::ITensorHandle> biasHandle =
nullptr;
3707 queueDescriptor.m_Weight = &weightTensor;
3708 queueDescriptor.m_Bias = &biasTensor;
3710 AddInputToWorkload(queueDescriptor, workloadInfo, inputInfo, inputHandle.get());
3711 AddInputToWorkload(queueDescriptor, workloadInfo, kernelInfo, weightsHandle.get());
3713 if (descriptor.m_BiasEnabled)
3716 AddInputToWorkload(queueDescriptor, workloadInfo, biasInfo, biasHandle.get());
3719 AddOutputToWorkload(queueDescriptor, workloadInfo, outputInfo, outputHandle.get());
3724 inputHandle->Allocate();
3725 outputHandle->Allocate();
3726 weightsHandle->Allocate();
3728 if (descriptor.m_BiasEnabled)
3730 biasHandle->Allocate();
3737 ExecuteWorkload(*workload, memoryManager);
3743 outputHandle->GetShape(),
3744 outputInfo.GetShape());
3748 armnn::IWorkloadFactory& workloadFactory,
3749 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3750 armnn::IWorkloadFactory& refWorkloadFactory,
3751 const armnn::ITensorHandleFactory& tensorHandleFactory,
3752 const armnn::ITensorHandleFactory& refTensorHandleFactory)
3754 return CompareConvolution2dTestImpl<armnn::DataType::Float32>(
3755 workloadFactory, memoryManager, refWorkloadFactory, tensorHandleFactory, refTensorHandleFactory);
3759 armnn::IWorkloadFactory& workloadFactory,
3760 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3761 const armnn::ITensorHandleFactory& tensorHandleFactory,
3765 return DepthwiseConvolution2dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3766 workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled, layout);
3770 armnn::IWorkloadFactory& workloadFactory,
3771 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3772 const armnn::ITensorHandleFactory& tensorHandleFactory,
3775 return DepthwiseConvolution2dNhwcTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3776 workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled);
3780 armnn::IWorkloadFactory& workloadFactory,
3781 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3782 const armnn::ITensorHandleFactory& tensorHandleFactory,
3786 return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3787 workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled, layout);
3791 armnn::IWorkloadFactory& workloadFactory,
3792 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3793 const armnn::ITensorHandleFactory& tensorHandleFactory)
3796 std::vector<float> input = { 1.f, 2.f, 3.f, 4.f };
3798 std::vector<float> kernelData;
3799 std::vector<float> singleDepthKernel{ 1.f, -1.f, -1.f, 1.f };
3800 for (
unsigned int i = 0; i < 64; ++i)
3802 kernelData.insert(kernelData.end(), singleDepthKernel.begin(), singleDepthKernel.end());
3809 std::vector<float> kernelPermuted(kernelTensorInfo.GetNumElements());
3811 kernelData.data(), kernelPermuted.data(),
3814 std::vector<float> expectedOutputData(64, 0.f);
3817 return DepthwiseConvolution2dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3820 tensorHandleFactory,
3823 std::vector<float>(),
3825 inputTensorInfo.GetShape(),
3826 kernelTensorInfo.GetShape(),
3827 outputTensorInfo.GetShape(),
3834 armnn::IWorkloadFactory& workloadFactory,
3835 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3836 const armnn::ITensorHandleFactory& tensorHandleFactory,
3840 return DepthwiseConvolution2dAsymmetricTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3841 workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled, layout);
3845 armnn::IWorkloadFactory& workloadFactory,
3846 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3847 const armnn::ITensorHandleFactory& tensorHandleFactory,
3851 return DepthwiseConvolution2dTestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3852 workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3856 armnn::IWorkloadFactory& workloadFactory,
3857 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3858 const armnn::ITensorHandleFactory& tensorHandleFactory,
3862 return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3863 workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3867 armnn::IWorkloadFactory& workloadFactory,
3868 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3869 const armnn::ITensorHandleFactory& tensorHandleFactory)
3871 return SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3874 tensorHandleFactory,
3881 armnn::IWorkloadFactory& workloadFactory,
3882 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3883 const armnn::ITensorHandleFactory& tensorHandleFactory,
3887 return DepthwiseConvolution2dTestImpl<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3888 workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3892 armnn::IWorkloadFactory& workloadFactory,
3893 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3894 const armnn::ITensorHandleFactory& tensorHandleFactory,
3898 return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3899 workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3903 armnn::IWorkloadFactory& workloadFactory,
3904 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
3905 const armnn::ITensorHandleFactory& tensorHandleFactory,
3908 using namespace armnn;
3910 const DataType inputType = DataType::QAsymmU8;
3911 const DataType kernelType = DataType::QSymmS8;
3912 const DataType biasType = DataType::Signed32;
3914 TensorInfo inputInfo ({ 1, 3, 3, 2 }, inputType, 0.5f, 128);
3915 TensorInfo outputInfo({ 1, 2, 2, 4 }, inputType, 1.0f, 128);
3917 const std::vector<float> quantScales{ 1.0f, 0.5f, 1.0f, 0.5f };
3918 const unsigned int quantDimension = 3;
3919 TensorInfo kernelInfo({ 1, 2, 2, 4 }, kernelType, quantScales, quantDimension);
3921 const std::vector<float> biasQuantScales{ 0.5f, 0.25f, 0.5f, 0.25f };
3922 constexpr
unsigned int biasQuantDimension = 0;
3923 TensorInfo biasInfo({ 4 }, biasType, biasQuantScales, biasQuantDimension);
3925 std::vector<uint8_t> inputData =
3938 std::vector<int8_t> kernelData =
3951 std::vector<int8_t> tmp(kernelData.size());
3953 armnnUtils::Permute(kernelInfo.GetShape(), {0, 2, 3, 1}, kernelData.data(), tmp.data(),
sizeof(int8_t));
3958 std::vector<int32_t> biasData =
3963 std::vector<uint8_t> expectedOutputData =
3977 std::vector<uint8_t> actualOutput(outputInfo.GetNumElements());
3981 descriptor.m_StrideY = 1;
3982 descriptor.m_PadLeft = 0;
3983 descriptor.m_PadRight = 0;
3984 descriptor.m_PadTop = 0;
3985 descriptor.m_PadBottom = 0;
3986 descriptor.m_DilationX = 1;
3987 descriptor.m_DilationY = 1;
3988 descriptor.m_BiasEnabled =
true;
3989 descriptor.m_DataLayout = layout;
3991 std::unique_ptr<ITensorHandle> inputHandle = tensorHandleFactory.
CreateTensorHandle(inputInfo);
3992 std::unique_ptr<ITensorHandle> weightsHandle = tensorHandleFactory.
CreateTensorHandle(kernelInfo);
3993 std::unique_ptr<ITensorHandle> biasHandle = tensorHandleFactory.
CreateTensorHandle(biasInfo);
3994 std::unique_ptr<ITensorHandle> outputHandle = tensorHandleFactory.
CreateTensorHandle(outputInfo);
4001 AddInputToWorkload(queueDescriptor, workloadInfo, inputInfo, inputHandle.get());
4002 AddInputToWorkload(queueDescriptor, workloadInfo, kernelInfo, weightsHandle.get());
4003 AddOutputToWorkload(queueDescriptor, workloadInfo, outputInfo, outputHandle.get());
4004 AddInputToWorkload(queueDescriptor, workloadInfo, biasInfo, biasHandle.get());
4016 queueDescriptor.
m_Weight = &weightTensor;
4017 queueDescriptor.
m_Bias = &biasTensor;
4022 inputHandle->Allocate();
4023 outputHandle->Allocate();
4027 ExecuteWorkload(*workload, memoryManager);
4035 outputHandle->GetShape(),
4036 outputInfo.GetShape());
4040 armnn::IWorkloadFactory& workloadFactory,
4041 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
4042 armnn::IWorkloadFactory& refWorkloadFactory,
4043 const armnn::ITensorHandleFactory& tensorHandleFactory,
4044 const armnn::ITensorHandleFactory& refTensorHandleFactory,
4047 return CompareDepthwiseConvolution2dTestImpl<armnn::DataType::Float32>(
4048 workloadFactory, memoryManager, refWorkloadFactory, tensorHandleFactory, refTensorHandleFactory, layout);
4052 armnn::IWorkloadFactory& workloadFactory,
4053 const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager,
4054 armnn::IWorkloadFactory& refWorkloadFactory,
4055 const armnn::ITensorHandleFactory& tensorHandleFactory,
4056 const armnn::ITensorHandleFactory& refTensorHandleFactory,
4059 return CompareDepthwiseConvolution2dTestImpl<armnn::DataType::QAsymmU8>(
4060 workloadFactory, memoryManager, refWorkloadFactory, tensorHandleFactory, refTensorHandleFactory, layout);
LayerTestResult< T, 4 > DepthwiseConvolution2dMult2Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
LayerTestResult< float, 4 > Convolution2d3x3Stride2x2BFloat16Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout &dataLayout)
uint32_t m_PadBottom
Padding bottom value in the height dimension.
bool m_BiasEnabled
Enable/disable bias.
LayerTestResult< O, 4 > SimpleConvolution2dNhwcTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const std::vector< T > &input, const std::vector< T > &kernel, const std::vector< B > &bias, const std::vector< O > &outputExpected, const armnn::TensorShape &inputShape, const armnn::TensorShape &kernelShape, const armnn::TensorShape &outputExpectedShape, const armnn::DataLayout dataLayout, float qScale, int32_t qOffset, uint32_t padLeft=1, uint32_t padTop=1, uint32_t padRight=1, uint32_t padBottom=1, uint32_t strideX=1, uint32_t strideY=1)
std::vector< T > GetBias(bool biasEnabled, float qScale, armnn::TensorInfo outputInfo, armnn::DataLayout layout)
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dUint8Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
virtual const BackendId & GetBackendId() const =0
void PermuteTensorNhwcToNchw(armnn::TensorInfo &tensorInfo, std::vector< T > &tensorData)
bool m_BiasEnabled
Enable/disable bias.
LayerTestResult< int16_t, 4 > SimpleConvolution2d3x5QSymm16Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
LayerTestResult< T, 4 > SimpleConvolution2d3x3Stride2x2TestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, float qScale, int32_t qOffset, bool biasEnabled, const armnn::DataLayout &dataLayout)
LayerTestResult< T, 4 > Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::DataLayout layout, float qScale, int32_t qOffset)
const TensorShape & GetShape() const
uint32_t m_PadBottom
Padding bottom value in the height dimension.
LayerTestResult< float, 4 > Convolution2d3x3Stride2x2BFloat16SmallValueTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout &dataLayout)
void ApplyBias(std::vector< T > &v, float vScale, int32_t vOffset, const std::vector< B > &bias, float bScale, int32_t bOffset, uint32_t w, uint32_t h)
std::vector< T > GetBias8(bool biasEnabled, float qScale)
LayerTestResult< T, 4 > Convolution2d2x3x3Dilation3x3Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
LayerTestResult< uint8_t, 4 > SimpleConvolution2d3x5Uint8Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
A Convolution2dDescriptor for the Convolution2dLayer.
uint32_t m_PadLeft
Padding left value in the width dimension.
LayerTestResult< T, 4 > CompareConvolution2dTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory)
LayerTestResult< T, 4 > Convolution2d3x3DilationTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const std::vector< float > &inputNoQuantizedValues, armnn::TensorInfo &inputTensorInfo, const std::vector< float > &kernelNoQuantizedValues, armnn::TensorInfo &kernelTensorInfo, const std::vector< float > &outputExpectedNoQuantizedValues, armnn::TensorInfo &outputTensorInfo, uint32_t dilationX, uint32_t dilationY, armnn::DataLayout layout=armnn::DataLayout::NCHW, uint32_t padLeft=0, uint32_t padTop=0, uint32_t padRight=0, uint32_t padBottom=0, uint32_t strideX=1, uint32_t strideY=1, bool biasEnabled=false)
LayerTestResult< float, 4 > SimpleConvolution2d3x3NhwcTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
LayerTestResult< T, 4 > DepthwiseConvolution2dDepthMul1TestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, float qScale, int32_t qOffset, bool biasEnabled, const armnn::DataLayout layout)
const ConstTensorHandle * m_Weight
typename ResolveTypeImpl< DT >::Type ResolveType
const ConstTensorHandle * m_Bias
LayerTestResult< T, 4 > SimpleConvolution2d3x3NhwcTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, float qScale, int32_t qOffset, bool biasEnabled, armnn::DataLayout dataLayout)
LayerTestResult< T, 4 > DepthwiseConvolution2dTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, float qScale, int32_t qOffset, bool biasEnabled, const armnn::DataLayout layout)
uint32_t m_PadRight
Padding right value in the width dimension.
LayerTestResult< uint8_t, 4 > Convolution1dUint8Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
LayerTestResult< T, 4 > SimpleConvolution2dAsymmetricPaddingTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::DataLayout layout, float qScale, int32_t qOffset)
Copyright (c) 2021 ARM Limited and Contributors.
void IgnoreUnused(Ts &&...)
LayerTestResult< T, 4 > DepthwiseConvolution2dAsymmetricTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const std::vector< T > &input, const std::vector< T > &kernel, const std::vector< B > &bias, const std::vector< T > &outputExpected, const armnn::TensorShape &inputShape, const armnn::TensorShape &kernelShape, const armnn::TensorShape &outputExpectedShape, float qScale, int32_t qOffset, const armnn::DataLayout layout, uint32_t padLeft=0, uint32_t padTop=0, uint32_t padRight=0, uint32_t padBottom=0, uint32_t strideX=1, uint32_t strideY=1)
LayerTestResult< float, 4 > Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, armnn::DataLayout layout)
uint32_t m_DilationY
Dilation along y axis.
LayerDescriptor m_Parameters
void AllocateAndCopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
uint32_t m_DilationY
Dilation factor value for height dimension.
LayerTestResult< T, 4 > DepthwiseConvolution2dMult4Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
void SetShape(const TensorShape &newShape)
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthMul64Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory)
LayerTestResult< int16_t, 4 > SimpleConvolution2d3x3QSymm16Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
uint32_t m_PadTop
Padding top value in the height dimension.
void Permute(const armnn::TensorShape &dstShape, const armnn::PermutationVector &mappings, const void *src, void *dst, size_t dataTypeSize)
LayerTestResult< T, 4 > DepthwiseConvolution2dAsymmetricTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, float qScale, int32_t qOffset, bool biasEnabled, const armnn::DataLayout layout)
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
LayerTestResult< T, 4 > DepthwiseConvolution2d3x3Dilation3x3Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dDepthMul1Uint8Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
uint32_t m_DilationX
Dilation factor value for width dimension.
uint32_t m_PadTop
Padding top value in the height dimension.
#define ARMNN_ASSERT_MSG(COND, MSG)
std::shared_ptr< IMemoryManager > IMemoryManagerSharedPtr
int32_t GetQuantizationOffset() const
LayerTestResult< T, 4 > DepthwiseConvolution2d3x3DilationTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const std::vector< float > &inputNoQuantizedValues, armnn::TensorInfo &inputTensorInfo, const std::vector< float > &kernelNoQuantizedValues, armnn::TensorInfo &kernelTensorInfo, const std::vector< float > &outputExpectedNoQuantizedValues, armnn::TensorInfo &outputTensorInfo, uint32_t dilationX, uint32_t dilationY, armnn::DataLayout layout=armnn::DataLayout::NCHW, bool biasEnabled=false)
float GetQuantizationScale() const
Provides access to the appropriate indexes for Channels, Height and Width based on DataLayout...
LayerTestResult< T, 4 > DepthwiseConvolution2d2x3x3Dilation3x3Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
LayerTestResult< T, 4 > SimpleConvolution2dTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const std::vector< T > &originalInput, const std::vector< T > &originalKernel, const std::vector< B > &bias, const std::vector< T > &originalOutputExpected, const armnn::TensorShape &originalInputShape, const armnn::TensorShape &originalKernelShape, const armnn::TensorShape &originalOutputExpectedShape, float qScale, int32_t qOffset, const armnn::DataLayout layout=armnn::DataLayout::NCHW, uint32_t padLeft=0, uint32_t padTop=0, uint32_t padRight=0, uint32_t padBottom=0, uint32_t strideX=1, uint32_t strideY=1, uint32_t dilationX=1, uint32_t dilationY=1)
const ConstTensorHandle * m_Bias
void CopyDataFromITensorHandle(void *mem, const armnn::ITensorHandle *tensorHandle)
LayerTestResult< float, 4 > SimpleConvolution2d3x5Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
void SetQuantizationScale(float scale)
#define ARMNN_ASSERT(COND)
armnn::DataLayout GetDataLayout() const
LayerTestResult< T, 4 > CompareDepthwiseConvolution2dTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory, const armnnUtils::DataLayoutIndexed &layout)
const ConstTensorHandle * m_Weight
uint32_t m_StrideY
Stride value when proceeding through input for the height dimension.
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthMul1Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
DataType GetBiasDataType(DataType inputDataType)
LayerTestResult< uint8_t, 4 > SimpleConvolution2d3x3Uint8Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
LayerTestResult< float, 4 > Convolution2dAsymmetricPaddingTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, armnn::DataLayout layout)
LayerTestResult< float, 4 > SimpleConvolution2d3x3Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
LayerTestResult< T, 4 > Convolution2d3x3Dilation3x3Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
uint32_t m_DilationX
Dilation along x axis.
LayerTestResult< float, 4 > Convolution1dTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
LayerTestResult< T, 4 > SimpleConvolution2d3x5TestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, float qScale, int32_t qOffset, bool biasEnabled, const armnn::DataLayout layout)
uint32_t m_StrideY
Stride value when proceeding through input for the height dimension.
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dPerAxisQuantTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::DataLayout layout)
void CopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
LayerTestResult< T, 4 > DepthwiseConvolution2dNhwcTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, float qScale, int32_t qOffset, bool biasEnabled)
LayerTestResult< T, 4 > Convolution1dTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, float qScale, int32_t qOffset, bool biasEnabled)
LayerTestResult< int16_t, 4 > DepthwiseConvolution2dDepthMul1Int16Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
std::enable_if_t< std::is_unsigned< Source >::value &&std::is_unsigned< Dest >::value, Dest > numeric_cast(Source source)
armnn::TensorInfo GetTensorInfo(unsigned int numberOfBatches, unsigned int numberOfChannels, unsigned int height, unsigned int width, const armnn::DataLayout dataLayout, const armnn::DataType dataType)
LayerTestResult< float, 4 > DepthwiseConvolution2dAsymmetricTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthNhwcTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
Contains information about TensorInfos of a layer.
LayerTestResult< float, 4 > CompareDepthwiseConvolution2dFloatTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory, const armnn::DataLayout layout)
float SelectiveDequantize(T value, float scale, int32_t offset)
LayerTestResult< float, 4 > SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory)
void SetQuantizationOffset(int32_t offset)
LayerTestResult< uint8_t, 4 > Convolution2dPerAxisQuantTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::DataLayout layout)
LayerTestResult< float, 4 > CompareConvolution2dTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory)
LayerTestResult< T, 4 > SimpleConvolution2d3x3TestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, float qScale, int32_t qOffset, bool biasEnabled, const armnn::DataLayout layout)
LayerTestResult< T, 4 > SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, float qScale, int32_t qOffset, bool biasEnabled)
LayerTestResult< int16_t, 4 > DepthwiseConvolution2dInt16Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
std::vector< T > GetBias4(bool biasEnabled, float qScale)
virtual std::unique_ptr< IWorkload > CreateWorkload(LayerType type, const QueueDescriptor &descriptor, const WorkloadInfo &info) const
unsigned int GetChannelsIndex() const
LayerTestResult< uint8_t, 4 > CompareDepthwiseConvolution2dUint8Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory, const armnn::DataLayout layout)
armnn::TensorShape Permuted(const armnn::TensorShape &srcShape, const armnn::PermutationVector &mappings)
virtual std::unique_ptr< ITensorHandle > CreateTensorHandle(const TensorInfo &tensorInfo) const =0
LayerTestResult< float, 4 > DepthwiseConvolution2dTest(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
A DepthwiseConvolution2dDescriptor for the DepthwiseConvolution2dLayer.
Depthwise Convolution 2D layer workload data.
uint32_t m_PadLeft
Padding left value in the width dimension.
unsigned int GetNumElements() const
LayerTestResult< float, 4 > SimpleConvolution2d3x3Stride2x2Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
constexpr unsigned int GetDataTypeSize(DataType dataType)
LayerTestResult< T, 4 > Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
uint32_t m_PadRight
Padding right value in the width dimension.
std::vector< T > GetBias2(bool biasEnabled, float qScale)