ArmNN
 21.05
RefConvolution2dWorkload.cpp
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1 //
2 // Copyright © 2017 Arm Ltd. All rights reserved.
3 // SPDX-License-Identifier: MIT
4 //
5 
7 
8 #include "ConvImpl.hpp"
9 #include "RefWorkloadUtils.hpp"
10 
11 #include "Profiling.hpp"
12 
13 namespace armnn
14 {
16  const Convolution2dQueueDescriptor& descriptor, const WorkloadInfo& info)
17  : BaseWorkload<Convolution2dQueueDescriptor>(descriptor, info)
18 {
19  m_Weight = std::make_unique<ScopedTensorHandle>(*(descriptor.m_Weight));
20  const TensorInfo& rFilterInfo = m_Weight->GetTensorInfo();
21 
22  m_FilterShape = rFilterInfo.GetShape();
23  m_FilterDecoder = MakeDecoder<float>(rFilterInfo, m_Weight.get()->Map(true));
24 
25  if (descriptor.m_Parameters.m_BiasEnabled)
26  {
27  m_Bias = std::make_unique<ScopedTensorHandle>(*(descriptor.m_Bias));
28  const TensorInfo& biasInfo = m_Bias->GetTensorInfo();
29  m_BiasDecoder = MakeDecoder<float>(biasInfo, m_Bias->Map(true));
30  }
31 }
32 
34 {
36 }
37 
39 {
40  Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
41 }
42 
43 void RefConvolution2dWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const {
44  ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefConvolution2dWorkload_Execute");
45 
46  std::unique_ptr<Decoder<float>> inputDecoder = MakeDecoder<float>(GetTensorInfo(inputs[0]), inputs[0]->Map());
47  std::unique_ptr<Encoder<float>> outputEncoder = MakeEncoder<float>(GetTensorInfo(outputs[0]), outputs[0]->Map());
48 
49  const TensorShape& inputShape = GetTensorInfo(inputs[0]).GetShape();
50  const TensorShape& outputShape = GetTensorInfo(outputs[0]).GetShape();
51 
52  Convolve(inputShape, *inputDecoder, outputShape, *outputEncoder, m_FilterShape,
53  *m_FilterDecoder, m_Data.m_Parameters.m_BiasEnabled, m_BiasDecoder.get(),
57 }
58 
59 } //namespace armnn
bool m_BiasEnabled
Enable/disable bias.
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
const TensorShape & GetShape() const
Definition: Tensor.hpp:187
CPU Execution: Reference C++ kernels.
const ConstTensorHandle * m_Weight
const ConstTensorHandle * m_Bias
Copyright (c) 2021 ARM Limited and Contributors.
uint32_t m_DilationY
Dilation along y axis.
#define ARMNN_SCOPED_PROFILING_EVENT(backendId, name)
Definition: Profiling.hpp:173
uint32_t m_PadTop
Padding top value in the height dimension.
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
RefConvolution2dWorkload(const Convolution2dQueueDescriptor &descriptor, const WorkloadInfo &info)
void Convolve(const TensorShape &rInputShape, Decoder< float > &rInputDecoder, const TensorShape &rOutputShape, Encoder< float > &rOutputEncoder, const TensorShape &rFilterShape, Decoder< float > &rFilterDecoder, bool biasEnabled, Decoder< float > *pBiasDecoder, DataLayout dataLayout, unsigned int paddingTop, unsigned int paddingLeft, unsigned int xStride, unsigned int yStride, unsigned int xDilation, unsigned int yDilation, bool depthwise)
Definition: ConvImpl.cpp:71
uint32_t m_StrideY
Stride value when proceeding through input for the height dimension.
uint32_t m_DilationX
Dilation along x axis.
std::vector< ITensorHandle * > m_Outputs
Contains information about inputs and outputs to a layer.
std::vector< ITensorHandle * > m_Inputs
void ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor) override
const TensorInfo & GetTensorInfo(const ITensorHandle *tensorHandle)
float32 helpers
uint32_t m_PadLeft
Padding left value in the width dimension.