ArmNN
 21.02
RefDepthwiseConvolution2dWorkload.cpp
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1 //
2 // Copyright © 2017 Arm Ltd. All rights reserved.
3 // SPDX-License-Identifier: MIT
4 //
5 
7 
8 #include "ConvImpl.hpp"
9 #include "RefWorkloadUtils.hpp"
10 #include "Decoders.hpp"
11 #include "Encoders.hpp"
12 #include "Profiling.hpp"
13 #include <ResolveType.hpp>
14 
15 namespace armnn
16 {
17 
19  const DepthwiseConvolution2dQueueDescriptor& descriptor, const WorkloadInfo& info)
21 {
22  m_Weight = std::make_unique<ScopedCpuTensorHandle>(*(descriptor.m_Weight));
23  const TensorInfo& rFilterInfo = m_Weight->GetTensorInfo();
24  m_FilterShape = rFilterInfo.GetShape();
25  m_FilterDecoder = MakeDecoder<float>(rFilterInfo, m_Weight->Map(true));
26 
27  if (descriptor.m_Parameters.m_BiasEnabled)
28  {
29  m_Bias = std::make_unique<ScopedCpuTensorHandle>(*(descriptor.m_Bias));
30  const TensorInfo& biasInfo = m_Bias->GetTensorInfo();
31  m_BiasDecoder = MakeDecoder<float>(biasInfo, m_Bias->Map(true));
32  }
33 }
34 
36 {
37  const TensorInfo& inputInfo = GetTensorInfo(m_Data.m_Inputs[0]);
38  m_InputShape = inputInfo.GetShape();
39  m_InputDecoder = MakeDecoder<float>(inputInfo);
40 
41  const TensorInfo& outputInfo = GetTensorInfo(m_Data.m_Outputs[0]);
42  m_OutputShape = outputInfo.GetShape();
43  m_OutputEncoder = MakeEncoder<float>(outputInfo);
44 }
45 
47 {
48  ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefDepthwiseConvolution2dWorkload_Execute");
49  std::unique_ptr<Decoder<float>> pBiasDecoder{};
50 
51  m_InputDecoder->Reset(m_Data.m_Inputs[0]->Map());
52  m_OutputEncoder->Reset(m_Data.m_Outputs[0]->Map());
53 
54  Convolve(m_InputShape, *m_InputDecoder, m_OutputShape, *m_OutputEncoder,
55  m_FilterShape, *m_FilterDecoder, m_Data.m_Parameters.m_BiasEnabled, m_BiasDecoder.get(),
60 }
61 
62 } //namespace armnn
bool m_BiasEnabled
Enable/disable bias.
const TensorShape & GetShape() const
Definition: Tensor.hpp:187
CPU Execution: Reference C++ kernels.
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
uint32_t m_PadLeft
Padding left value in the width dimension.
const DepthwiseConvolution2dQueueDescriptor m_Data
Definition: Workload.hpp:46
Copyright (c) 2021 ARM Limited and Contributors.
uint32_t m_DilationY
Dilation factor value for height dimension.
#define ARMNN_SCOPED_PROFILING_EVENT(backendId, name)
Definition: Profiling.hpp:173
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
void Convolve(const TensorShape &rInputShape, Decoder< float > &rInputDecoder, const TensorShape &rOutputShape, Encoder< float > &rOutputEncoder, const TensorShape &rFilterShape, Decoder< float > &rFilterDecoder, bool biasEnabled, Decoder< float > *pBiasDecoder, DataLayout dataLayout, unsigned int paddingTop, unsigned int paddingLeft, unsigned int xStride, unsigned int yStride, unsigned int xDilation, unsigned int yDilation, bool depthwise)
Definition: ConvImpl.cpp:71
uint32_t m_DilationX
Dilation factor value for width dimension.
uint32_t m_PadTop
Padding top value in the height dimension.
RefDepthwiseConvolution2dWorkload(const DepthwiseConvolution2dQueueDescriptor &descriptor, const WorkloadInfo &info)
uint32_t m_StrideY
Stride value when proceeding through input for the height dimension.
std::vector< ITensorHandle * > m_Outputs
Contains information about inputs and outputs to a layer.
std::vector< ITensorHandle * > m_Inputs
const TensorInfo & GetTensorInfo(const ITensorHandle *tensorHandle)
float32 helpers