ArmNN
 21.02
Functions
Conv2dTestImpl.hpp File Reference
#include "LayerTestResult.hpp"
#include <ResolveType.hpp>
#include <armnn/Types.hpp>
#include <armnn/backends/IBackendInternal.hpp>
#include <backendsCommon/WorkloadFactory.hpp>

Go to the source code of this file.

Functions

template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > Convolution2d3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > Convolution2d2x3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x5Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x3Stride2x2Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x3NhwcTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
 
LayerTestResult< uint8_t, 4 > SimpleConvolution2d3x5Uint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > SimpleConvolution2d3x3Uint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > SimpleConvolution2d3x5QSymm16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > SimpleConvolution2d3x3QSymm16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution2dAsymmetricPaddingTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution1dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
 
LayerTestResult< uint8_t, 4 > Convolution1dUint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
 
LayerTestResult< float, 4 > CompareConvolution2dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory)
 
LayerTestResult< uint8_t, 4 > Convolution2dPerAxisQuantTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution2d3x3Stride2x2BFloat16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout &dataLayout)
 
LayerTestResult< float, 4 > Convolution2d3x3Stride2x2BFloat16SmallValueTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout &dataLayout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2d3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2d2x3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2dMult4Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2dMult2Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
template<typename T >
LayerTestResult< T, 4 > CompareDepthwiseConvolution2dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthNhwcTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthMul1Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthMul64Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dAsymmetricTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory)
 
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dUint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dDepthMul1Uint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > DepthwiseConvolution2dInt16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > DepthwiseConvolution2dDepthMul1Int16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dPerAxisQuantTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > CompareDepthwiseConvolution2dFloatTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > CompareDepthwiseConvolution2dUint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::ITensorHandleFactory &refTensorHandleFactory, const armnn::DataLayout layout)
 

Function Documentation

◆ CompareConvolution2dTest()

LayerTestResult<float, 4> CompareConvolution2dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::ITensorHandleFactory &  refTensorHandleFactory 
)

Definition at line 3534 of file Conv2dTestImpl.cpp.

3540 {
3541  return CompareConvolution2dTestImpl<armnn::DataType::Float32>(
3542  workloadFactory, memoryManager, refWorkloadFactory, tensorHandleFactory, refTensorHandleFactory);
3543 }

◆ CompareDepthwiseConvolution2dFloatTest()

LayerTestResult<float, 4> CompareDepthwiseConvolution2dFloatTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::ITensorHandleFactory &  refTensorHandleFactory,
const armnn::DataLayout  layout 
)

Definition at line 3789 of file Conv2dTestImpl.cpp.

3796 {
3797  return CompareDepthwiseConvolution2dTestImpl<armnn::DataType::Float32>(
3798  workloadFactory, memoryManager, refWorkloadFactory, tensorHandleFactory, refTensorHandleFactory, layout);
3799 }

◆ CompareDepthwiseConvolution2dTest()

LayerTestResult<T, 4> CompareDepthwiseConvolution2dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::ITensorHandleFactory &  refTensorHandleFactory,
const armnn::DataLayout  layout 
)

◆ CompareDepthwiseConvolution2dUint8Test()

LayerTestResult<uint8_t, 4> CompareDepthwiseConvolution2dUint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::ITensorHandleFactory &  refTensorHandleFactory,
const armnn::DataLayout  layout 
)

Definition at line 3801 of file Conv2dTestImpl.cpp.

3808 {
3809  return CompareDepthwiseConvolution2dTestImpl<armnn::DataType::QAsymmU8>(
3810  workloadFactory, memoryManager, refWorkloadFactory, tensorHandleFactory, refTensorHandleFactory, layout);
3811 }

◆ Convolution1dTest()

LayerTestResult<float, 4> Convolution1dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled 
)

Definition at line 3419 of file Conv2dTestImpl.cpp.

3424 {
3425  return Convolution1dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3426  workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled);
3427 }

◆ Convolution1dUint8Test()

LayerTestResult<uint8_t, 4> Convolution1dUint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled 
)

Definition at line 3429 of file Conv2dTestImpl.cpp.

3434 {
3435  return Convolution1dTestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3436  workloadFactory, memoryManager, tensorHandleFactory, 0.1f, 128, biasEnabled);
3437 }

◆ Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test()

LayerTestResult<T, 4> Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 1232 of file Conv2dTestImpl.cpp.

1238 {
1239  armnn::TensorInfo inputTensorInfo({1, 1, 10, 10}, ArmnnType);
1240  std::vector<float> inputNoQuantizedValues =
1241  {
1242  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1243  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1244  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1245  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1246  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1247  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1248  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1249  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1250  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1251  1, 1, 1, 1, 1, 1, 1, 1, 1, 1
1252  };
1253 
1254  armnn::TensorInfo kernelTensorInfo({ 1, 1, 2, 2}, ArmnnType);
1255  std::vector<float> kernelNoQuantizedValues =
1256  {
1257  1, 2,
1258  3, 4
1259  };
1260 
1261  // Since the dilation rate is 2 this will dilate the kernel to be like 3x3: d(K-1)+1 --> 2 x (2-1) + 1 = 3,
1262  // therefore the output will be 4x4: (I − K + 2P)/S +1 => trunc ( (10 - 3 + 2x2 ) / 3 + 1 )
1263  // where, dilation size = d = 2; kernel size = K = 2; input size = I = 10; padding size = P = 2; stride = S = 3
1264  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
1265  std::vector<float> outputExpectedNoQuantizedValues =
1266  {
1267  4, 7, 7, 3,
1268  6, 10, 10, 4,
1269  6, 10, 10, 4,
1270  2, 3, 3, 1
1271  };
1272  uint32_t padLeft = 1;
1273  uint32_t padTop = 1;
1274  uint32_t padRight = 1;
1275  uint32_t padBottom = 1;
1276 
1277  return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1278  workloadFactory,
1279  memoryManager,
1280  tensorHandleFactory,
1281  inputNoQuantizedValues,
1282  inputTensorInfo,
1283  kernelNoQuantizedValues,
1284  kernelTensorInfo,
1285  outputExpectedNoQuantizedValues,
1286  outputTensorInfo,
1287  2,
1288  2,
1289  layout,
1290  padLeft,
1291  padTop,
1292  padRight,
1293  padBottom,
1294  3,
1295  3,
1296  biasEnabled
1297  );
1298 }

◆ Convolution2d2x3x3Dilation3x3Test()

LayerTestResult<T, 4> Convolution2d2x3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 1159 of file Conv2dTestImpl.cpp.

1165 {
1166  armnn::TensorInfo inputTensorInfo({1, 2, 10, 10}, ArmnnType);
1167  std::vector<float> inputNoQuantizedValues =
1168  {
1169  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1170  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1171  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1172  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1173  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1174  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1175  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1176  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1177  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1178  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1179 
1180  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1181  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1182  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1183  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1184  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1185  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1186  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1187  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1188  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1189  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1190  };
1191 
1192  armnn::TensorInfo kernelTensorInfo({ 1, 2, 3, 3}, ArmnnType);
1193  std::vector<float> kernelNoQuantizedValues =
1194  {
1195  1, 2, 3,
1196  4, 5, 6,
1197  7, 8, 9,
1198 
1199  1, 2, 3,
1200  4, 5, 6,
1201  7, 8, 9
1202  };
1203 
1204  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
1205  // therefore the output will be 4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
1206  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
1207  std::vector<float> outputExpectedNoQuantizedValues =
1208  {
1209  12., 10., 10., 10.,
1210  12., 10., 10., 10.,
1211  12., 10., 10., 10.,
1212  6., 4., 4., 4.
1213  };
1214 
1215  return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1216  workloadFactory,
1217  memoryManager,
1218  tensorHandleFactory,
1219  inputNoQuantizedValues,
1220  inputTensorInfo,
1221  kernelNoQuantizedValues,
1222  kernelTensorInfo,
1223  outputExpectedNoQuantizedValues,
1224  outputTensorInfo,
1225  3,
1226  3,
1227  layout,
1228  biasEnabled);
1229 }

◆ Convolution2d3x3Dilation3x3Test()

LayerTestResult<T, 4> Convolution2d3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 1101 of file Conv2dTestImpl.cpp.

1107 {
1108  armnn::TensorInfo inputTensorInfo({1, 1, 10, 10}, ArmnnType);
1109  std::vector<float> inputNoQuantizedValues =
1110  {
1111  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1112  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1113  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1114  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1115  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1116  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1117  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1118  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1119  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1120  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1121  };
1122 
1123  armnn::TensorInfo kernelTensorInfo({ 1, 1, 3, 3}, ArmnnType);
1124  std::vector<float> kernelNoQuantizedValues =
1125  {
1126  1, 2, 3,
1127  4, 5, 6,
1128  7, 8, 9
1129  };
1130 
1131  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
1132  // therefore the output will be 4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
1133  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
1134  std::vector<float> outputExpectedNoQuantizedValues =
1135  {
1136  6., 5., 5., 5.,
1137  6., 5., 5., 5.,
1138  6., 5., 5., 5.,
1139  3., 2., 2., 2.
1140  };
1141 
1142  return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1143  workloadFactory,
1144  memoryManager,
1145  tensorHandleFactory,
1146  inputNoQuantizedValues,
1147  inputTensorInfo,
1148  kernelNoQuantizedValues,
1149  kernelTensorInfo,
1150  outputExpectedNoQuantizedValues,
1151  outputTensorInfo,
1152  3,
1153  3,
1154  layout,
1155  biasEnabled);
1156 }

◆ Convolution2d3x3Stride2x2BFloat16SmallValueTest()

LayerTestResult<float, 4> Convolution2d3x3Stride2x2BFloat16SmallValueTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout &  dataLayout 
)

Definition at line 1511 of file Conv2dTestImpl.cpp.

References armnn::BFloat16, armnn::Float32, armnn::IgnoreUnused(), and SimpleConvolution2dNhwcTestImpl().

1517 {
1518  // BFloat16 input and weight, Float32 output
1519  armnn::IgnoreUnused(biasEnabled);
1520 
1521  // Input is a single-batch, 1 channel, 5x5 image.
1522  armnn::TensorInfo inputDesc({1, 5, 5, 1}, armnn::DataType::BFloat16);
1523 
1524  std::vector<armnn::BFloat16> inputValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1525  {
1526  0.0367984f, // 0.0368652
1527  0.0380895f, // 0.0380859
1528  0.0420157f, // 0.0419922
1529  0.0675631f, // 0.0673828
1530  0.0938920f, // 0.09375
1531  0.0476106f, // 0.0476074
1532  0.1035490f, // 0.103516
1533  0.1260370f, // 0.125977
1534  0.0461647f, // 0.0461426
1535  0.0883828f, // 0.0883789
1536  0.1159540f, // 0.115723
1537  0.0498519f, // 0.0498047
1538  0.0104630f, // 0.010437
1539  0.0154114f, // 0.0154419
1540  0.00137681f, // 0.00137329
1541  0.0344238f, // 0.0344616
1542  0.0356445f, // 0.0355693
1543  0.0495605f, // 0.0495018
1544  0.0683594f, // 0.0683308
1545  0.0991211f, // 0.0988837
1546  0.0461426f, // 0.0461838
1547  0.0996094f, // 0.0997546
1548  0.1269530f, // 0.127099
1549  0.0393066f, // 0.0392791
1550  0.103516f // 0.103641
1551  },
1552  1.0f, 0);
1553 
1554  auto input = MakeTensor<armnn::BFloat16, 4>(inputDesc, inputValues);
1555 
1556  // Use a 3x3 kernel.
1557  armnn::TensorInfo kernelDesc({1, 3, 3, 1}, armnn::DataType::BFloat16);
1558 
1559  std::vector<armnn::BFloat16> kernelValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1560  {
1561  -0.126184f, // -0.125977
1562  -0.150468f, // -0.150391
1563  -0.101412f, // -0.101562
1564  -0.0586369f,// -0.0585938
1565  -0.0865864f,// -0.0864258
1566  -0.0435089f,// -0.043457
1567  0.0347555f, // 0.034668
1568  0.0323111f, // 0.0322266
1569  0.0385381f // 0.0385742
1570  },
1571  1.0f, 0);
1572 
1573  auto kernel = MakeTensor<armnn::BFloat16, 4>(kernelDesc, kernelValues);
1574 
1575  // Expected output is a single-batch, 1 channel, 3x3 image.
1576  armnn::TensorInfo outputDesc({1, 3, 3, 1}, armnn::DataType::Float32);
1577 
1578  // Expected output (with results if calculated as FP32 in the comments)
1579  const std::vector<float> outputData =
1580  {
1581  0.000686645508f, // 0.000685
1582  0.000640869141f, // 0.000639
1583  -0.00759887695f, // -0.007631
1584  -0.02734375f, // -0.027388
1585  -0.0356445312f, // -0.035737
1586  -0.0145874023f, // -0.014568
1587  -0.0170898438f, // -0.017124
1588  -0.0373535156f, // -0.037431
1589  -0.0346679688f // -0.034808
1590  };
1591 
1592  boost::multi_array<float, 4> expectedOutput = MakeTensor<float, 4>(outputDesc, outputData);
1593 
1594  uint32_t padLeft = 1;
1595  uint32_t padTop = 1;
1596  uint32_t padRight = 1;
1597  uint32_t padBottom = 1;
1598  uint32_t strideX = 2;
1599  uint32_t strideY = 2;
1600 
1601  return SimpleConvolution2dNhwcTestImpl
1602  <armnn::DataType::BFloat16, armnn::DataType::Float32, armnn::BFloat16, float, armnn::DataType::Float32, float>(
1603  workloadFactory,
1604  memoryManager,
1605  tensorHandleFactory,
1606  input,
1607  kernel,
1608  boost::multi_array<float, 1>(),
1609  expectedOutput,
1610  dataLayout,
1611  1.0f,
1612  0,
1613  padLeft,
1614  padTop,
1615  padRight,
1616  padBottom,
1617  strideX,
1618  strideY);
1619 }
armnn::IgnoreUnused
void IgnoreUnused(Ts &&...)
Definition: IgnoreUnused.hpp:14
SimpleConvolution2dNhwcTestImpl
LayerTestResult< O, 4 > SimpleConvolution2dNhwcTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const boost::multi_array< T, 4 > &input, const boost::multi_array< T, 4 > &kernel, const boost::multi_array< B, 1 > &bias, const boost::multi_array< O, 4 > &outputExpected, const armnn::DataLayout dataLayout, float qScale, int32_t qOffset, uint32_t padLeft=1, uint32_t padTop=1, uint32_t padRight=1, uint32_t padBottom=1, uint32_t strideX=1, uint32_t strideY=1)
Definition: Conv2dTestImpl.cpp:368

◆ Convolution2d3x3Stride2x2BFloat16Test()

LayerTestResult<float, 4> Convolution2d3x3Stride2x2BFloat16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout &  dataLayout 
)

Definition at line 1401 of file Conv2dTestImpl.cpp.

References armnn::BFloat16, armnn::Float32, armnn::IgnoreUnused(), and SimpleConvolution2dNhwcTestImpl().

1407 {
1408  // BFloat16 input and weight, Float32 output
1409  armnn::IgnoreUnused(biasEnabled);
1410 
1411  // Input is a single-batch, 1 channel, 5x5 image.
1412  armnn::TensorInfo inputDesc({1, 5, 5, 1}, armnn::DataType::BFloat16);
1413 
1414  std::vector<armnn::BFloat16> inputValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1415  {
1416  10.0367984f, // 10.0625
1417  2.0380895f, // 2.03125
1418  15.0420157f, // 15.0625
1419  22.0675631f, // 22.125
1420  8.0938920f, // 8.125
1421  5.0476106f, // 5.0625
1422  80.1035490f, // 80
1423  100.1260370f, // 100
1424  55.0461647f, // 55
1425  120.0883828f, // 120
1426  9.1159540f, // 9.125
1427  90.0498519f, // 90
1428  200.0104630f, // 200
1429  30.0154114f, // 30
1430  75.00137681f, // 75
1431  30.0344238f, // 30
1432  25.0356445f, // 25
1433  130.0495605f, // 130
1434  60.0683594f, // 60
1435  35.0991211f, // 35
1436  8.0461426f, // 8.0625
1437  12.0996094f, // 12.125
1438  98.1269530f, // 98
1439  125.0393066f, // 125
1440  5.103516f // 5.0937
1441  },
1442  1.0f, 0);
1443 
1444  auto input = MakeTensor<armnn::BFloat16, 4>(inputDesc, inputValues);
1445 
1446  // Use a 3x3 kernel.
1447  armnn::TensorInfo kernelDesc({1, 3, 3, 1}, armnn::DataType::BFloat16);
1448 
1449  std::vector<armnn::BFloat16> kernelValues = armnnUtils::QuantizedVector<armnn::BFloat16>(
1450  {
1451  -0.126184f, // -0.125977
1452  -0.150468f, // -0.150391
1453  -0.101412f, // -0.101562
1454  -0.0586369f,// -0.0585938
1455  -0.0865864f,// -0.0864258
1456  -0.0435089f,// -0.043457
1457  0.0347555f, // 0.034668
1458  0.0323111f, // 0.0322266
1459  0.0385381f // 0.0385742
1460  },
1461  1.0f, 0);
1462 
1463  auto kernel = MakeTensor<armnn::BFloat16, 4>(kernelDesc, kernelValues);
1464 
1465  // Expected output is a single-batch, 1 channel, 3x3 image.
1466  armnn::TensorInfo outputDesc({1, 3, 3, 1}, armnn::DataType::Float32);
1467 
1468  // Expected output (with results if calculated as FP32 in the comments)
1469  const std::vector<float> outputData =
1470  {
1471  2.296875f, // 2.29240716
1472  5.75f, // 5.75851926
1473  3.78125f, // 3.79855026
1474  -11.625f, // -11.65498118
1475  -47.25f, // -47.27316893
1476  -30.0f, // -30.04771684
1477  -8.25f, // -8.28126168
1478  -43.5f, // -43.46531337
1479  -20.625f // -20.63477281
1480  };
1481 
1482  boost::multi_array<float, 4> expectedOutput = MakeTensor<float, 4>(outputDesc, outputData);
1483 
1484  uint32_t padLeft = 1;
1485  uint32_t padTop = 1;
1486  uint32_t padRight = 1;
1487  uint32_t padBottom = 1;
1488  uint32_t strideX = 2;
1489  uint32_t strideY = 2;
1490 
1491  return SimpleConvolution2dNhwcTestImpl
1492  <armnn::DataType::BFloat16, armnn::DataType::Float32, armnn::BFloat16, float, armnn::DataType::Float32, float>(
1493  workloadFactory,
1494  memoryManager,
1495  tensorHandleFactory,
1496  input,
1497  kernel,
1498  boost::multi_array<float, 1>(),
1499  expectedOutput,
1500  dataLayout,
1501  1.0f,
1502  0,
1503  padLeft,
1504  padTop,
1505  padRight,
1506  padBottom,
1507  strideX,
1508  strideY);
1509 }
armnn::IgnoreUnused
void IgnoreUnused(Ts &&...)
Definition: IgnoreUnused.hpp:14
SimpleConvolution2dNhwcTestImpl
LayerTestResult< O, 4 > SimpleConvolution2dNhwcTestImpl(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const boost::multi_array< T, 4 > &input, const boost::multi_array< T, 4 > &kernel, const boost::multi_array< B, 1 > &bias, const boost::multi_array< O, 4 > &outputExpected, const armnn::DataLayout dataLayout, float qScale, int32_t qOffset, uint32_t padLeft=1, uint32_t padTop=1, uint32_t padRight=1, uint32_t padBottom=1, uint32_t strideX=1, uint32_t strideY=1)
Definition: Conv2dTestImpl.cpp:368

◆ Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest()

LayerTestResult<float, 4> Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
armnn::DataLayout  layout 
)

Definition at line 3408 of file Conv2dTestImpl.cpp.

References Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon(), and armnn::Float32.

3413 {
3414  return Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon
3415  <armnn::DataType::Float32, armnn::DataType::Float32>(
3416  workloadFactory, memoryManager, tensorHandleFactory, layout, 0.0f, 0);
3417 }
Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon
LayerTestResult< T, 4 > Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::ITensorHandleFactory &tensorHandleFactory, const armnn::DataLayout layout, float qScale, int32_t qOffset)
Definition: Conv2dTestImpl.cpp:880

◆ Convolution2dAsymmetricPaddingTest()

LayerTestResult<float, 4> Convolution2dAsymmetricPaddingTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
armnn::DataLayout  layout 
)

Definition at line 3398 of file Conv2dTestImpl.cpp.

3403 {
3404  return SimpleConvolution2dAsymmetricPaddingTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3405  workloadFactory, memoryManager, tensorHandleFactory, layout, 0.0f, 0);
3406 }

◆ Convolution2dPerAxisQuantTest()

LayerTestResult<uint8_t, 4> Convolution2dPerAxisQuantTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::DataLayout  layout 
)

Definition at line 3439 of file Conv2dTestImpl.cpp.

References AllocateAndCopyDataToITensorHandle(), CopyDataFromITensorHandle(), CopyDataToITensorHandle(), IWorkloadFactory::CreateConvolution2d(), ITensorHandleFactory::CreateTensorHandle(), Convolution2dDescriptor::m_BiasEnabled, Convolution2dDescriptor::m_DataLayout, Convolution2dDescriptor::m_PadBottom, Convolution2dDescriptor::m_PadLeft, Convolution2dDescriptor::m_PadRight, Convolution2dDescriptor::m_PadTop, QueueDescriptorWithParameters< LayerDescriptor >::m_Parameters, Convolution2dDescriptor::m_StrideX, Convolution2dDescriptor::m_StrideY, armnn::NCHW, LayerTestResult< T, n >::output, LayerTestResult< T, n >::outputExpected, and PermuteTensorNhwcToNchw().

3444 {
3445  using namespace armnn;
3446 
3447  const DataType inputType = DataType::QAsymmU8;
3448  const DataType kernelType = DataType::QSymmS8;
3449  const DataType biasType = DataType::Signed32;
3450 
3451  TensorInfo inputInfo ({ 1, 3, 1, 2 }, inputType, 0.5f, 128);
3452  TensorInfo outputInfo({ 1, 3, 1, 3 }, inputType, 1.0f, 128);
3453 
3454  const std::vector<float> quantScales{ 0.5f, 0.75f, 1.0f };
3455  constexpr unsigned int quantDimension = 0;
3456 
3457  TensorInfo kernelInfo({ 3, 1, 1, 2 }, kernelType, quantScales, quantDimension);
3458 
3459  const std::vector<float> biasQuantScales{ 0.25f, 0.375f, 0.5f };
3460  TensorInfo biasInfo({ 3 }, biasType, biasQuantScales, quantDimension);
3461 
3462  std::vector<uint8_t> inputData =
3463  {
3464  138, 108, 138, 108, 138, 108
3465  };
3466 
3467  std::vector<int8_t> kernelData =
3468  {
3469  1, 2, 1, 2, 1, 2
3470  };
3471 
3472  std::vector<int32_t> biasData =
3473  {
3474  4, 4, 4
3475  };
3476 
3477  std::vector<uint8_t> expectedOutputData =
3478  {
3479  121, 118, 115, 121, 118, 115, 121, 118, 115
3480  };
3481 
3482  if (layout == DataLayout::NCHW)
3483  {
3484  PermuteTensorNhwcToNchw(inputInfo, inputData);
3485  PermuteTensorNhwcToNchw(kernelInfo, kernelData);
3486  PermuteTensorNhwcToNchw(outputInfo, expectedOutputData);
3487  }
3488 
3489  Convolution2dDescriptor descriptor;
3490  descriptor.m_StrideX = 1;
3491  descriptor.m_StrideY = 1;
3492  descriptor.m_PadLeft = 0;
3493  descriptor.m_PadRight = 0;
3494  descriptor.m_PadTop = 0;
3495  descriptor.m_PadBottom = 0;
3496  descriptor.m_BiasEnabled = true;
3497  descriptor.m_DataLayout = layout;
3498 
3499 
3500  std::unique_ptr<ITensorHandle> inputHandle = tensorHandleFactory.CreateTensorHandle(inputInfo);
3501  std::unique_ptr<ITensorHandle> outputHandle = tensorHandleFactory.CreateTensorHandle(outputInfo);
3502 
3503 
3504  WorkloadInfo workloadInfo;
3505  ScopedCpuTensorHandle weightTensor(kernelInfo);
3506  ScopedCpuTensorHandle biasTensor(biasInfo);
3507 
3508  AllocateAndCopyDataToITensorHandle(&weightTensor, kernelData.data());
3509  AllocateAndCopyDataToITensorHandle(&biasTensor, biasData.data());
3510 
3511  Convolution2dQueueDescriptor queueDescriptor;
3512  queueDescriptor.m_Parameters = descriptor;
3513  queueDescriptor.m_Weight = &weightTensor;
3514  queueDescriptor.m_Bias = &biasTensor;
3515 
3516  AddInputToWorkload(queueDescriptor, workloadInfo, inputInfo, inputHandle.get());
3517  AddOutputToWorkload(queueDescriptor, workloadInfo, outputInfo, outputHandle.get());
3518 
3519  std::unique_ptr<IWorkload> workload = workloadFactory.CreateConvolution2d(queueDescriptor, workloadInfo);
3520  inputHandle->Allocate();
3521  outputHandle->Allocate();
3522 
3523  CopyDataToITensorHandle(inputHandle.get(), inputData.data());
3524 
3525  ExecuteWorkload(*workload, memoryManager);
3526 
3527  LayerTestResult<uint8_t, 4> ret(outputInfo);
3528  CopyDataFromITensorHandle(ret.output.origin(), outputHandle.get());
3529  ret.outputExpected = MakeTensor<uint8_t, 4>(outputInfo, expectedOutputData);
3530 
3531  return ret;
3532 }
armnn::Convolution2dDescriptor::m_PadBottom
uint32_t m_PadBottom
Padding bottom value in the height dimension.
Definition: Descriptors.hpp:444
armnn::Convolution2dDescriptor::m_BiasEnabled
bool m_BiasEnabled
Enable/disable bias.
Definition: Descriptors.hpp:454
armnn::Convolution2dDescriptor::m_DataLayout
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
Definition: Descriptors.hpp:456
armnn::Convolution2dDescriptor
A Convolution2dDescriptor for the Convolution2dLayer.
Definition: Descriptors.hpp:408
armnn::Convolution2dDescriptor::m_PadRight
uint32_t m_PadRight
Padding right value in the width dimension.
Definition: Descriptors.hpp:440
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_software_tools.dox:6
armnn::Convolution2dDescriptor::m_PadTop
uint32_t m_PadTop
Padding top value in the height dimension.
Definition: Descriptors.hpp:442
armnn::Convolution2dDescriptor::m_StrideX
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
Definition: Descriptors.hpp:446
armnn::DataType
DataType
Definition: Types.hpp:32
AllocateAndCopyDataToITensorHandle
void AllocateAndCopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:19
CopyDataFromITensorHandle
void CopyDataFromITensorHandle(void *memory, const armnn::ITensorHandle *tensorHandle)
Definition: TensorCopyUtils.cpp:14
armnn::Convolution2dDescriptor::m_StrideY
uint32_t m_StrideY
Stride value when proceeding through input for the height dimension.
Definition: Descriptors.hpp:448
armnn::WorkloadInfo
Contains information about inputs and outputs to a layer.
Definition: WorkloadInfo.hpp:16
armnn::ITensorHandleFactory::CreateTensorHandle
virtual std::unique_ptr< ITensorHandle > CreateTensorHandle(const TensorInfo &tensorInfo) const =0
armnn::Convolution2dDescriptor::m_PadLeft
uint32_t m_PadLeft
Padding left value in the width dimension.
Definition: Descriptors.hpp:438
armnn::IWorkloadFactory::CreateConvolution2d
virtual std::unique_ptr< IWorkload > CreateConvolution2d(const Convolution2dQueueDescriptor &descriptor, const WorkloadInfo &info) const
Definition: WorkloadFactory.cpp:1368
CopyDataToITensorHandle
void CopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:9
PermuteTensorNhwcToNchw
void PermuteTensorNhwcToNchw(armnn::TensorInfo &tensorInfo, std::vector< T > &tensorData)
Definition: DataLayoutUtils.hpp:26

◆ DepthwiseConvolution2d2x3x3Dilation3x3Test()

LayerTestResult<T, 4> DepthwiseConvolution2d2x3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2693 of file Conv2dTestImpl.cpp.

2699 {
2700  armnn::TensorInfo inputTensorInfo({1, 2, 10, 10}, ArmnnType);
2701  std::vector<float> inputNoQuantizedValues =
2702  {
2703  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2704  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2705  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2706  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2707  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2708  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2709  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2710  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2711  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2712  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2713 
2714  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2715  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2716  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2717  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2718  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2719  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2720  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2721  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2722  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2723  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2724  };
2725 
2726  armnn::TensorInfo kernelTensorInfo({ 1, 2, 3, 3}, ArmnnType);
2727  std::vector<float> kernelNoQuantizedValues =
2728  {
2729  1, 2, 3,
2730  4, 5, 6,
2731  7, 8, 9,
2732 
2733  1, 2, 3,
2734  4, 5, 6,
2735  7, 8, 9
2736  };
2737 
2738  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
2739  // therefore the output will be 2x4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
2740  armnn::TensorInfo outputTensorInfo({ 1, 2, 4, 4}, ArmnnType);
2741  std::vector<float> outputExpectedNoQuantizedValues =
2742  {
2743  6., 5., 5., 5.,
2744  6., 5., 5., 5.,
2745  6., 5., 5., 5.,
2746  3., 2., 2., 2.,
2747 
2748  6., 5., 5., 5.,
2749  6., 5., 5., 5.,
2750  6., 5., 5., 5.,
2751  3., 2., 2., 2.
2752  };
2753 
2754  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2755  workloadFactory,
2756  memoryManager,
2757  tensorHandleFactory,
2758  inputNoQuantizedValues,
2759  inputTensorInfo,
2760  kernelNoQuantizedValues,
2761  kernelTensorInfo,
2762  outputExpectedNoQuantizedValues,
2763  outputTensorInfo,
2764  3,
2765  3,
2766  layout,
2767  biasEnabled);
2768 }

◆ DepthwiseConvolution2d3x3Dilation3x3Test()

LayerTestResult<T, 4> DepthwiseConvolution2d3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2635 of file Conv2dTestImpl.cpp.

2641 {
2642  armnn::TensorInfo inputTensorInfo({1, 1, 10, 10}, ArmnnType);
2643  std::vector<float> inputNoQuantizedValues =
2644  {
2645  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2646  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2647  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2648  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2649  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2650  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2651  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2652  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2653  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2654  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2655  };
2656 
2657  armnn::TensorInfo kernelTensorInfo({ 1, 1, 3, 3}, ArmnnType);
2658  std::vector<float> kernelNoQuantizedValues =
2659  {
2660  1, 2, 3,
2661  4, 5, 6,
2662  7, 8, 9
2663  };
2664 
2665  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
2666  // therefore the output will be 4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
2667  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
2668  std::vector<float> outputExpectedNoQuantizedValues =
2669  {
2670  6., 5., 5., 5.,
2671  6., 5., 5., 5.,
2672  6., 5., 5., 5.,
2673  3., 2., 2., 2.
2674  };
2675 
2676  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2677  workloadFactory,
2678  memoryManager,
2679  tensorHandleFactory,
2680  inputNoQuantizedValues,
2681  inputTensorInfo,
2682  kernelNoQuantizedValues,
2683  kernelTensorInfo,
2684  outputExpectedNoQuantizedValues,
2685  outputTensorInfo,
2686  3,
2687  3,
2688  layout,
2689  biasEnabled);
2690 }

◆ DepthwiseConvolution2dAsymmetricTest()

LayerTestResult<float, 4> DepthwiseConvolution2dAsymmetricTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3611 of file Conv2dTestImpl.cpp.

3617 {
3618  return DepthwiseConvolution2dAsymmetricTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3619  workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled, layout);
3620 }

◆ DepthwiseConvolution2dDepthMul1Int16Test()

LayerTestResult<int16_t, 4> DepthwiseConvolution2dDepthMul1Int16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3669 of file Conv2dTestImpl.cpp.

3675 {
3676  return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3677  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3678 }

◆ DepthwiseConvolution2dDepthMul1Test()

LayerTestResult<float, 4> DepthwiseConvolution2dDepthMul1Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3566 of file Conv2dTestImpl.cpp.

3572 {
3573  return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3574  workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled, layout);
3575 }

◆ DepthwiseConvolution2dDepthMul1Uint8Test()

LayerTestResult<uint8_t, 4> DepthwiseConvolution2dDepthMul1Uint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3633 of file Conv2dTestImpl.cpp.

3639 {
3640  return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3641  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3642 }

◆ DepthwiseConvolution2dDepthMul64Test()

LayerTestResult<float, 4> DepthwiseConvolution2dDepthMul64Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory 
)

Definition at line 3577 of file Conv2dTestImpl.cpp.

References armnn::Float32, and armnn::NCHW.

3581 {
3582  armnn::TensorInfo inputTensorInfo({ 1, 1, 2, 2 }, armnn::DataType::Float32);
3583  auto input = MakeTensor<float, 4>(inputTensorInfo, { 1.f, 2.f, 3.f, 4.f });
3584 
3585  std::vector<float> kernelData;
3586  std::vector<float> singleDepthKernel{ 1.f, -1.f, -1.f, 1.f };
3587  for (unsigned int i = 0; i < 64; ++i)
3588  {
3589  kernelData.insert(kernelData.end(), singleDepthKernel.begin(), singleDepthKernel.end());
3590  }
3591  armnn::TensorInfo kernelTensorInfo({ 64, 1, 2, 2 }, armnn::DataType::Float32);
3592  auto kernel = MakeTensor<float, 4>(kernelTensorInfo, kernelData);
3593 
3594  std::vector<float> expectedOutputData(64, 0.f);
3595  armnn::TensorInfo outputTensorInfo({ 1, 64, 1, 1 }, armnn::DataType::Float32);
3596  auto expectedOutput = MakeTensor<float, 4>(outputTensorInfo, expectedOutputData);
3597 
3598  return DepthwiseConvolution2dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3599  workloadFactory,
3600  memoryManager,
3601  tensorHandleFactory,
3602  input,
3603  kernel,
3604  boost::multi_array<float, 1>(),
3605  expectedOutput,
3606  0.f,
3607  0,
3608  armnn::DataLayout::NCHW);
3609 }

◆ DepthwiseConvolution2dDepthNhwcTest()

LayerTestResult<float, 4> DepthwiseConvolution2dDepthNhwcTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled 
)

Definition at line 3556 of file Conv2dTestImpl.cpp.

3561 {
3562  return DepthwiseConvolution2dNhwcTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3563  workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled);
3564 }

◆ DepthwiseConvolution2dInt16Test()

LayerTestResult<int16_t, 4> DepthwiseConvolution2dInt16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3658 of file Conv2dTestImpl.cpp.

3664 {
3665  return DepthwiseConvolution2dTestImpl<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3666  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3667 }

◆ DepthwiseConvolution2dMult2Test()

LayerTestResult<T, 4> DepthwiseConvolution2dMult2Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2865 of file Conv2dTestImpl.cpp.

2871 {
2872  armnn::TensorInfo inputTensorInfo({1, 2, 3, 3}, ArmnnType);
2873  std::vector<float> inputNoQuantizedValues =
2874  {
2875  10.0, 10.0, 10.0,
2876  10.0, 10.0, 10.0,
2877  10.0, 10.0, 10.0,
2878 
2879  21.0, 22.0, 23.0,
2880  24.0, 25.0, 26.0,
2881  27.0, 28.0, 29.0
2882  };
2883 
2884  armnn::TensorInfo kernelTensorInfo({ 2, 2, 2, 2}, ArmnnType);
2885 
2886  std::vector<float> kernelNoQuantizedValues =
2887  {
2888  0.25f, 0.25f,
2889  0.25f, 0.25f,
2890 
2891  0.2f , 0.0f,
2892  0.0f , 0.0f,
2893 
2894  0.0f , 0.0f,
2895  0.0f , 0.1f,
2896 
2897  0.0f , 0.3f,
2898  0.0f , 0.0f
2899 
2900  };
2901 
2902  armnn::TensorInfo outputTensorInfo({ 1, 4, 2, 2}, ArmnnType);
2903  std::vector<float> outputExpectedNoQuantizedValues =
2904  {
2905  10.f, 10.f,
2906  10.f, 10.f,
2907 
2908  1.f, 1.f,
2909  1.f, 1.f,
2910 
2911  4.2000003f, 4.4f,
2912  4.8f, 5.f,
2913 
2914  6.6000004f, 6.9f,
2915  7.5000005f, 7.8f
2916  };
2917 
2918 
2919  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2920  workloadFactory,
2921  memoryManager,
2922  tensorHandleFactory,
2923  inputNoQuantizedValues,
2924  inputTensorInfo,
2925  kernelNoQuantizedValues,
2926  kernelTensorInfo,
2927  outputExpectedNoQuantizedValues,
2928  outputTensorInfo,
2929  1,
2930  1,
2931  layout,
2932  biasEnabled);
2933 }

◆ DepthwiseConvolution2dMult4Test()

LayerTestResult<T, 4> DepthwiseConvolution2dMult4Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2771 of file Conv2dTestImpl.cpp.

2777 {
2778  armnn::TensorInfo inputTensorInfo({1, 2, 3, 3}, ArmnnType);
2779  std::vector<float> inputNoQuantizedValues =
2780  {
2781  10.0, 10.0, 10.0,
2782  10.0, 10.0, 10.0,
2783  10.0, 10.0, 10.0,
2784 
2785  21.0, 22.0, 23.0,
2786  24.0, 25.0, 26.0,
2787  27.0, 28.0, 29.0
2788  };
2789 
2790  armnn::TensorInfo kernelTensorInfo({ 4, 2, 2, 2}, ArmnnType);
2791 
2792  std::vector<float> kernelNoQuantizedValues =
2793  {
2794  0.25f, 0.25f,
2795  0.25f, 0.25f,
2796 
2797  0.25f, 0.25f,
2798  0.25f, 0.25f,
2799 
2800  0.0f , 0.0f,
2801  0.0f , 0.1f,
2802 
2803  0.0f , 0.0f,
2804  0.0f , 0.1f,
2805 
2806  0.2f , 0.0f,
2807  0.0f , 0.0f,
2808 
2809  0.2f , 0.0f,
2810  0.0f , 0.0f,
2811 
2812  0.0f , 0.3f,
2813  0.0f , 0.0f,
2814 
2815  0.0f , 0.3f,
2816  0.0f , 0.0f
2817  };
2818 
2819  armnn::TensorInfo outputTensorInfo({ 1, 8, 2, 2}, ArmnnType);
2820  std::vector<float> outputExpectedNoQuantizedValues =
2821  {
2822  10.f, 10.f,
2823  10.f, 10.f,
2824 
2825  1.f, 1.f,
2826  1.f, 1.f,
2827 
2828  2.f, 2.f,
2829  2.f, 2.f,
2830 
2831  3.f, 3.f,
2832  3.f, 3.f,
2833 
2834  23.f, 24.f,
2835  26.f, 27.f,
2836 
2837  2.5f, 2.6000001f,
2838  2.8f, 2.9f,
2839 
2840  4.2000003f, 4.4f,
2841  4.8f, 5.f,
2842 
2843  6.6000004f, 6.9f,
2844  7.5000005f, 7.8f
2845  };
2846 
2847 
2848  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2849  workloadFactory,
2850  memoryManager,
2851  tensorHandleFactory,
2852  inputNoQuantizedValues,
2853  inputTensorInfo,
2854  kernelNoQuantizedValues,
2855  kernelTensorInfo,
2856  outputExpectedNoQuantizedValues,
2857  outputTensorInfo,
2858  1,
2859  1,
2860  layout,
2861  biasEnabled);
2862 }

◆ DepthwiseConvolution2dPerAxisQuantTest()

LayerTestResult<uint8_t, 4> DepthwiseConvolution2dPerAxisQuantTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
const armnn::DataLayout  layout 
)

Definition at line 3680 of file Conv2dTestImpl.cpp.

References AllocateAndCopyDataToITensorHandle(), CopyDataFromITensorHandle(), CopyDataToITensorHandle(), IWorkloadFactory::CreateDepthwiseConvolution2d(), ITensorHandleFactory::CreateTensorHandle(), DepthwiseConvolution2dDescriptor::m_BiasEnabled, DepthwiseConvolution2dDescriptor::m_DataLayout, DepthwiseConvolution2dDescriptor::m_DilationX, DepthwiseConvolution2dDescriptor::m_DilationY, DepthwiseConvolution2dDescriptor::m_PadBottom, DepthwiseConvolution2dDescriptor::m_PadLeft, DepthwiseConvolution2dDescriptor::m_PadRight, DepthwiseConvolution2dDescriptor::m_PadTop, QueueDescriptorWithParameters< LayerDescriptor >::m_Parameters, DepthwiseConvolution2dDescriptor::m_StrideX, DepthwiseConvolution2dDescriptor::m_StrideY, armnn::NCHW, LayerTestResult< T, n >::output, LayerTestResult< T, n >::outputExpected, and PermuteTensorNhwcToNchw().

3685 {
3686  using namespace armnn;
3687 
3688  const DataType inputType = DataType::QAsymmU8;
3689  const DataType kernelType = DataType::QSymmS8;
3690  const DataType biasType = DataType::Signed32;
3691 
3692  TensorInfo inputInfo ({ 1, 3, 3, 2 }, inputType, 0.5f, 128); // N H W C
3693  TensorInfo outputInfo({ 1, 2, 2, 4 }, inputType, 1.0f, 128); // N H W C
3694 
3695  const std::vector<float> quantScales{ 1.0f, 0.5f, 1.0f, 0.5f };
3696  const unsigned int quantDimension = 0;
3697  TensorInfo kernelInfo({ 2, 2, 2, 2 }, kernelType, quantScales, quantDimension); // M I H W
3698 
3699  const std::vector<float> biasQuantScales{ 0.5f, 0.25f, 0.5f, 0.25f };
3700  constexpr unsigned int biasQuantDimension = 0;
3701  TensorInfo biasInfo({ 4 }, biasType, biasQuantScales, biasQuantDimension);
3702 
3703  std::vector<uint8_t> inputData =
3704  {
3705  129, 130,
3706  129, 130,
3707  129, 130,
3708  129, 130,
3709  129, 130,
3710  129, 130,
3711  129, 130,
3712  129, 130,
3713  129, 130
3714  };
3715 
3716  std::vector<int8_t> kernelData =
3717  {
3718  1, 1, 1, 1,
3719  1, 1, 1, 1,
3720  1, 1, 1, 1,
3721  1, 1, 1, 1
3722  };
3723 
3724  std::vector<int32_t> biasData =
3725  {
3726  4, 4, 4, 4
3727  };
3728 
3729  std::vector<uint8_t> expectedOutputData =
3730  {
3731  132, 130, 134, 131,
3732  132, 130, 134, 131,
3733  132, 130, 134, 131,
3734  132, 130, 134, 131
3735  };
3736 
3737  if (layout == DataLayout::NCHW)
3738  {
3739  PermuteTensorNhwcToNchw(inputInfo, inputData);
3740  PermuteTensorNhwcToNchw(outputInfo, expectedOutputData);
3741  }
3742 
3743  DepthwiseConvolution2dDescriptor descriptor;
3744  descriptor.m_StrideX = 1;
3745  descriptor.m_StrideY = 1;
3746  descriptor.m_PadLeft = 0;
3747  descriptor.m_PadRight = 0;
3748  descriptor.m_PadTop = 0;
3749  descriptor.m_PadBottom = 0;
3750  descriptor.m_DilationX = 1;
3751  descriptor.m_DilationY = 1;
3752  descriptor.m_BiasEnabled = true;
3753  descriptor.m_DataLayout = layout;
3754 
3755  std::unique_ptr<ITensorHandle> inputHandle = tensorHandleFactory.CreateTensorHandle(inputInfo);
3756  std::unique_ptr<ITensorHandle> outputHandle = tensorHandleFactory.CreateTensorHandle(outputInfo);
3757 
3758  WorkloadInfo workloadInfo;
3759  ScopedCpuTensorHandle weightTensor(kernelInfo);
3760  ScopedCpuTensorHandle biasTensor(biasInfo);
3761 
3762  AllocateAndCopyDataToITensorHandle(&weightTensor, kernelData.data());
3763  AllocateAndCopyDataToITensorHandle(&biasTensor, biasData.data());
3764 
3765  DepthwiseConvolution2dQueueDescriptor queueDescriptor;
3766  queueDescriptor.m_Parameters = descriptor;
3767  queueDescriptor.m_Weight = &weightTensor;
3768  queueDescriptor.m_Bias = &biasTensor;
3769 
3770  AddInputToWorkload(queueDescriptor, workloadInfo, inputInfo, inputHandle.get());
3771  AddOutputToWorkload(queueDescriptor, workloadInfo, outputInfo, outputHandle.get());
3772 
3773  std::unique_ptr<IWorkload> workload = workloadFactory.CreateDepthwiseConvolution2d(queueDescriptor, workloadInfo);
3774  inputHandle->Allocate();
3775  outputHandle->Allocate();
3776 
3777  CopyDataToITensorHandle(inputHandle.get(), inputData.data());
3778 
3779  ExecuteWorkload(*workload, memoryManager);
3780 
3781  LayerTestResult<uint8_t, 4> ret(outputInfo);
3782 
3783  CopyDataFromITensorHandle(ret.output.origin(), outputHandle.get());
3784  ret.outputExpected = MakeTensor<uint8_t, 4>(outputInfo, expectedOutputData);
3785 
3786  return ret;
3787 }
armnn::DepthwiseConvolution2dDescriptor::m_BiasEnabled
bool m_BiasEnabled
Enable/disable bias.
Definition: Descriptors.hpp:506
armnn::DepthwiseConvolution2dDescriptor::m_PadBottom
uint32_t m_PadBottom
Padding bottom value in the height dimension.
Definition: Descriptors.hpp:496
armnn::DepthwiseConvolution2dDescriptor::m_DataLayout
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
Definition: Descriptors.hpp:508
armnn::DepthwiseConvolution2dDescriptor::m_PadLeft
uint32_t m_PadLeft
Padding left value in the width dimension.
Definition: Descriptors.hpp:490
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_software_tools.dox:6
armnn::DepthwiseConvolution2dDescriptor::m_DilationY
uint32_t m_DilationY
Dilation factor value for height dimension.
Definition: Descriptors.hpp:504
armnn::DepthwiseConvolution2dDescriptor::m_StrideX
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
Definition: Descriptors.hpp:498
armnn::DataType
DataType
Definition: Types.hpp:32
armnn::DepthwiseConvolution2dDescriptor::m_DilationX
uint32_t m_DilationX
Dilation factor value for width dimension.
Definition: Descriptors.hpp:502
armnn::DepthwiseConvolution2dDescriptor::m_PadTop
uint32_t m_PadTop
Padding top value in the height dimension.
Definition: Descriptors.hpp:494
AllocateAndCopyDataToITensorHandle
void AllocateAndCopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:19
CopyDataFromITensorHandle
void CopyDataFromITensorHandle(void *memory, const armnn::ITensorHandle *tensorHandle)
Definition: TensorCopyUtils.cpp:14
armnn::DepthwiseConvolution2dDescriptor::m_StrideY
uint32_t m_StrideY
Stride value when proceeding through input for the height dimension.
Definition: Descriptors.hpp:500
armnn::WorkloadInfo
Contains information about inputs and outputs to a layer.
Definition: WorkloadInfo.hpp:16
armnn::IWorkloadFactory::CreateDepthwiseConvolution2d
virtual std::unique_ptr< IWorkload > CreateDepthwiseConvolution2d(const DepthwiseConvolution2dQueueDescriptor &descriptor, const WorkloadInfo &info) const
Definition: WorkloadFactory.cpp:1386
armnn::ITensorHandleFactory::CreateTensorHandle
virtual std::unique_ptr< ITensorHandle > CreateTensorHandle(const TensorInfo &tensorInfo) const =0
armnn::DepthwiseConvolution2dDescriptor
A DepthwiseConvolution2dDescriptor for the DepthwiseConvolution2dLayer.
Definition: Descriptors.hpp:460
CopyDataToITensorHandle
void CopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:9
armnn::DepthwiseConvolution2dDescriptor::m_PadRight
uint32_t m_PadRight
Padding right value in the width dimension.
Definition: Descriptors.hpp:492
PermuteTensorNhwcToNchw
void PermuteTensorNhwcToNchw(armnn::TensorInfo &tensorInfo, std::vector< T > &tensorData)
Definition: DataLayoutUtils.hpp:26

◆ DepthwiseConvolution2dTest()

LayerTestResult<float, 4> DepthwiseConvolution2dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3545 of file Conv2dTestImpl.cpp.

3551 {
3552  return DepthwiseConvolution2dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3553  workloadFactory, memoryManager, tensorHandleFactory, 0.0f, 0, biasEnabled, layout);
3554 }

◆ DepthwiseConvolution2dUint8Test()

LayerTestResult<uint8_t, 4> DepthwiseConvolution2dUint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3622 of file Conv2dTestImpl.cpp.

3628 {
3629  return DepthwiseConvolution2dTestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3630  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3631 }

◆ SimpleConvolution2d3x3NhwcTest()

LayerTestResult<float, 4> SimpleConvolution2d3x3NhwcTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled 
)

Definition at line 3332 of file Conv2dTestImpl.cpp.

References armnn::NHWC.

3337 {
3338  return SimpleConvolution2d3x3NhwcTestCommon<armnn::DataType::Float32>(
3339  workloadFactory,
3340  memoryManager,
3341  tensorHandleFactory,
3342  0.f,
3343  0,
3344  biasEnabled,
3345  armnn::DataLayout::NHWC);
3346 }

◆ SimpleConvolution2d3x3QSymm16Test()

LayerTestResult<int16_t, 4> SimpleConvolution2d3x3QSymm16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3387 of file Conv2dTestImpl.cpp.

3393 {
3394  return SimpleConvolution2d3x3TestCommon<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3395  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3396 }

◆ SimpleConvolution2d3x3Stride2x2Test()

LayerTestResult<float, 4> SimpleConvolution2d3x3Stride2x2Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3348 of file Conv2dTestImpl.cpp.

3354 {
3355  return SimpleConvolution2d3x3Stride2x2TestCommon<armnn::DataType::Float32>(
3356  workloadFactory,
3357  memoryManager,
3358  tensorHandleFactory,
3359  0.f,
3360  0,
3361  biasEnabled,
3362  layout);
3363 }

◆ SimpleConvolution2d3x3Test()

LayerTestResult<float, 4> SimpleConvolution2d3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3321 of file Conv2dTestImpl.cpp.

3327 {
3328  return SimpleConvolution2d3x3TestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3329  workloadFactory, memoryManager, tensorHandleFactory, 0.f, 0, biasEnabled, layout);
3330 }

◆ SimpleConvolution2d3x3Uint8Test()

LayerTestResult<uint8_t, 4> SimpleConvolution2d3x3Uint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3365 of file Conv2dTestImpl.cpp.

3371 {
3372  return SimpleConvolution2d3x3TestCommon<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3373  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3374 }

◆ SimpleConvolution2d3x5QSymm16Test()

LayerTestResult<int16_t, 4> SimpleConvolution2d3x5QSymm16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3376 of file Conv2dTestImpl.cpp.

3382 {
3383  return SimpleConvolution2d3x5TestCommon<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3384  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3385 }

◆ SimpleConvolution2d3x5Test()

LayerTestResult<float, 4> SimpleConvolution2d3x5Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3299 of file Conv2dTestImpl.cpp.

3305 {
3306  return SimpleConvolution2d3x5TestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3307  workloadFactory, memoryManager, tensorHandleFactory, 0.f, 0, biasEnabled, layout);
3308 }

◆ SimpleConvolution2d3x5Uint8Test()

LayerTestResult<uint8_t, 4> SimpleConvolution2d3x5Uint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3310 of file Conv2dTestImpl.cpp.

3316 {
3317  return SimpleConvolution2d3x5TestCommon<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3318  workloadFactory, memoryManager, tensorHandleFactory, 0.5f, 50, biasEnabled, layout);
3319 }

◆ SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTest()

LayerTestResult<float, 4> SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::ITensorHandleFactory &  tensorHandleFactory 
)

Definition at line 3644 of file Conv2dTestImpl.cpp.

3648 {
3649  return SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3650  workloadFactory,
3651  memoryManager,
3652  tensorHandleFactory,
3653  0.f,
3654  0,
3655  false);
3656 }