ArmNN
 20.11
ClPooling2dWorkload.cpp
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1 //
2 // Copyright © 2017 Arm Ltd. All rights reserved.
3 // SPDX-License-Identifier: MIT
4 //
5 
7 #include <cl/ClLayerSupport.hpp>
8 #include <cl/ClTensorHandle.hpp>
11 
12 #include "ClWorkloadUtils.hpp"
13 
14 namespace armnn
15 {
16 using namespace armcomputetensorutils;
17 
19  const TensorInfo& output,
20  const Pooling2dDescriptor& descriptor)
21 {
22  const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout);
23  const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout);
24 
25  arm_compute::PoolingLayerInfo layerInfo = BuildArmComputePoolingLayerInfo(descriptor);
26 
27  return arm_compute::CLPoolingLayer::validate(&aclInputInfo, &aclOutputInfo, layerInfo);
28 }
29 
31  const Pooling2dQueueDescriptor& descriptor, const WorkloadInfo& info)
32  : BaseWorkload<Pooling2dQueueDescriptor>(descriptor, info)
33 {
34  m_Data.ValidateInputsOutputs("ClPooling2dWorkload", 1, 1);
35 
36  arm_compute::ICLTensor& input = static_cast<IClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
37  arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
38 
39  arm_compute::DataLayout aclDataLayout = ConvertDataLayout(m_Data.m_Parameters.m_DataLayout);
40  input.info()->set_data_layout(aclDataLayout);
41  output.info()->set_data_layout(aclDataLayout);
42 
43  // flag to use wider accumulators (32 bit instead of 16 for FP16) to improve accuracy
44  // enable fp_mixed_precision for the the FP16 cases that
45  // accumulation reaches a limit beyond which there is no more increment of the value
46  bool fpMixedPrecision = false;
47 
48  arm_compute::PoolingLayerInfo layerInfo = BuildArmComputePoolingLayerInfo(m_Data.m_Parameters, fpMixedPrecision);
49 
50  // Run the layer.
51  m_PoolingLayer.configure(&input, &output, layerInfo);
52 }
53 
55 {
56  ARMNN_SCOPED_PROFILING_EVENT_CL("ClPooling2dWorkload_Execute");
57  RunClFunction(m_PoolingLayer, CHECK_LOCATION());
58 }
59 
60 }
void Execute() const override
DataLayout
Definition: Types.hpp:50
ClPooling2dWorkload(const Pooling2dQueueDescriptor &descriptor, const WorkloadInfo &info)
#define ARMNN_SCOPED_PROFILING_EVENT_CL(name)
void RunClFunction(arm_compute::IFunction &function, const CheckLocation &location)
const Pooling2dQueueDescriptor m_Data
Definition: Workload.hpp:46
void ValidateInputsOutputs(const std::string &descName, unsigned int numExpectedIn, unsigned int numExpectedOut) const
Copyright (c) 2020 ARM Limited.
arm_compute::Status ClPooling2dWorkloadValidate(const TensorInfo &input, const TensorInfo &output, const Pooling2dDescriptor &descriptor)
Status
enumeration
Definition: Types.hpp:26
#define CHECK_LOCATION()
Definition: Exceptions.hpp:197
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
std::vector< ITensorHandle * > m_Outputs
Contains information about inputs and outputs to a layer.
std::vector< ITensorHandle * > m_Inputs
A Pooling2dDescriptor for the Pooling2dLayer.