ArmNN
 20.02
Functions
Conv2dTestImpl.hpp File Reference
#include "LayerTestResult.hpp"
#include <ResolveType.hpp>
#include <armnn/Types.hpp>
#include <armnn/backends/IBackendInternal.hpp>
#include <backendsCommon/WorkloadFactory.hpp>

Go to the source code of this file.

Functions

template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > Convolution2d3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > Convolution2d2x3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x5Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x3Stride2x2Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleConvolution2d3x3NhwcTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled)
 
LayerTestResult< uint8_t, 4 > SimpleConvolution2d3x5Uint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > SimpleConvolution2d3x3Uint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > SimpleConvolution2d3x5QSymm16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > SimpleConvolution2d3x3QSymm16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution2dAsymmetricPaddingTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::DataLayout layout)
 
LayerTestResult< float, 4 > Convolution1dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled)
 
LayerTestResult< uint8_t, 4 > Convolution1dUint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled)
 
LayerTestResult< float, 4 > CompareConvolution2dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory)
 
LayerTestResult< uint8_t, 4 > Convolution2dPerAxisQuantTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2d3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2d2x3x3Dilation3x3Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2dMult4Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
template<armnn::DataType ArmnnType, armnn::DataType ArmnnBType, typename T = armnn::ResolveType<ArmnnType>>
LayerTestResult< T, 4 > DepthwiseConvolution2dMult2Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
template<typename T >
LayerTestResult< T, 4 > CompareDepthwiseConvolution2dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthNhwcTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthMul1Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dDepthMul64Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager)
 
LayerTestResult< float, 4 > DepthwiseConvolution2dAsymmetricTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager)
 
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dUint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dDepthMul1Uint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > DepthwiseConvolution2dInt16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< int16_t, 4 > DepthwiseConvolution2dDepthMul1Int16Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, bool biasEnabled, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > DepthwiseConvolution2dPerAxisQuantTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::DataLayout layout)
 
LayerTestResult< float, 4 > CompareDepthwiseConvolution2dFloatTest (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::DataLayout layout)
 
LayerTestResult< uint8_t, 4 > CompareDepthwiseConvolution2dUint8Test (armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, armnn::IWorkloadFactory &refWorkloadFactory, const armnn::DataLayout layout)
 

Function Documentation

◆ CompareConvolution2dTest()

LayerTestResult<float, 4> CompareConvolution2dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory 
)

Definition at line 3184 of file Conv2dTestImpl.cpp.

3188 {
3189  return CompareConvolution2dTestImpl<armnn::DataType::Float32>(
3190  workloadFactory, memoryManager, refWorkloadFactory);
3191 }

◆ CompareDepthwiseConvolution2dFloatTest()

LayerTestResult<float, 4> CompareDepthwiseConvolution2dFloatTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::DataLayout  layout 
)

Definition at line 3424 of file Conv2dTestImpl.cpp.

3429 {
3430  return CompareDepthwiseConvolution2dTestImpl<armnn::DataType::Float32>(
3431  workloadFactory, memoryManager, refWorkloadFactory, layout);
3432 }

◆ CompareDepthwiseConvolution2dTest()

LayerTestResult<T, 4> CompareDepthwiseConvolution2dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::DataLayout  layout 
)

◆ CompareDepthwiseConvolution2dUint8Test()

LayerTestResult<uint8_t, 4> CompareDepthwiseConvolution2dUint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::IWorkloadFactory &  refWorkloadFactory,
const armnn::DataLayout  layout 
)

Definition at line 3434 of file Conv2dTestImpl.cpp.

3439 {
3440  return CompareDepthwiseConvolution2dTestImpl<armnn::DataType::QAsymmU8>(
3441  workloadFactory, memoryManager, refWorkloadFactory, layout);
3442 }

◆ Convolution1dTest()

LayerTestResult<float, 4> Convolution1dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled 
)

Definition at line 3074 of file Conv2dTestImpl.cpp.

3078 {
3079  return Convolution1dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3080  workloadFactory, memoryManager, 0.0f, 0, biasEnabled);
3081 }

◆ Convolution1dUint8Test()

LayerTestResult<uint8_t, 4> Convolution1dUint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled 
)

Definition at line 3083 of file Conv2dTestImpl.cpp.

3087 {
3088  return Convolution1dTestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3089  workloadFactory, memoryManager, 0.1f, 128, biasEnabled);
3090 }

◆ Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test()

LayerTestResult<T, 4> Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 1210 of file Conv2dTestImpl.cpp.

1215 {
1216  armnn::TensorInfo inputTensorInfo({1, 1, 10, 10}, ArmnnType);
1217  std::vector<float> inputNoQuantizedValues =
1218  {
1219  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1220  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1221  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1222  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1223  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1224  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1225  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1226  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1227  1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1228  1, 1, 1, 1, 1, 1, 1, 1, 1, 1
1229  };
1230 
1231  armnn::TensorInfo kernelTensorInfo({ 1, 1, 2, 2}, ArmnnType);
1232  std::vector<float> kernelNoQuantizedValues =
1233  {
1234  1, 2,
1235  3, 4
1236  };
1237 
1238  // Since the dilation rate is 2 this will dilate the kernel to be like 3x3: d(K-1)+1 --> 2 x (2-1) + 1 = 3,
1239  // therefore the output will be 4x4: (I − K + 2P)/S +1 => trunc ( (10 - 3 + 2x2 ) / 3 + 1 )
1240  // where, dilation size = d = 2; kernel size = K = 2; input size = I = 10; padding size = P = 2; stride = S = 3
1241  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
1242  std::vector<float> outputExpectedNoQuantizedValues =
1243  {
1244  4, 7, 7, 3,
1245  6, 10, 10, 4,
1246  6, 10, 10, 4,
1247  2, 3, 3, 1
1248  };
1249  uint32_t padLeft = 1;
1250  uint32_t padTop = 1;
1251  uint32_t padRight = 1;
1252  uint32_t padBottom = 1;
1253 
1254  return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1255  workloadFactory,
1256  memoryManager,
1257  inputNoQuantizedValues,
1258  inputTensorInfo,
1259  kernelNoQuantizedValues,
1260  kernelTensorInfo,
1261  outputExpectedNoQuantizedValues,
1262  outputTensorInfo,
1263  2,
1264  2,
1265  layout,
1266  padLeft,
1267  padTop,
1268  padRight,
1269  padBottom,
1270  3,
1271  3,
1272  biasEnabled
1273  );
1274 }

◆ Convolution2d2x3x3Dilation3x3Test()

LayerTestResult<T, 4> Convolution2d2x3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 1139 of file Conv2dTestImpl.cpp.

1144 {
1145  armnn::TensorInfo inputTensorInfo({1, 2, 10, 10}, ArmnnType);
1146  std::vector<float> inputNoQuantizedValues =
1147  {
1148  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1149  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1150  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1151  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1152  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1153  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1154  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1155  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1156  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1157  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1158 
1159  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1160  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1161  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1162  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1163  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1164  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1165  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1166  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1167  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1168  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1169  };
1170 
1171  armnn::TensorInfo kernelTensorInfo({ 1, 2, 3, 3}, ArmnnType);
1172  std::vector<float> kernelNoQuantizedValues =
1173  {
1174  1, 2, 3,
1175  4, 5, 6,
1176  7, 8, 9,
1177 
1178  1, 2, 3,
1179  4, 5, 6,
1180  7, 8, 9
1181  };
1182 
1183  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
1184  // therefore the output will be 4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
1185  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
1186  std::vector<float> outputExpectedNoQuantizedValues =
1187  {
1188  12., 10., 10., 10.,
1189  12., 10., 10., 10.,
1190  12., 10., 10., 10.,
1191  6., 4., 4., 4.
1192  };
1193 
1194  return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1195  workloadFactory,
1196  memoryManager,
1197  inputNoQuantizedValues,
1198  inputTensorInfo,
1199  kernelNoQuantizedValues,
1200  kernelTensorInfo,
1201  outputExpectedNoQuantizedValues,
1202  outputTensorInfo,
1203  3,
1204  3,
1205  layout,
1206  biasEnabled);
1207 }

◆ Convolution2d3x3Dilation3x3Test()

LayerTestResult<T, 4> Convolution2d3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 1083 of file Conv2dTestImpl.cpp.

1088 {
1089  armnn::TensorInfo inputTensorInfo({1, 1, 10, 10}, ArmnnType);
1090  std::vector<float> inputNoQuantizedValues =
1091  {
1092  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1093  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1094  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1095  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1096  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1097  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1098  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1099  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1100  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1101  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1102  };
1103 
1104  armnn::TensorInfo kernelTensorInfo({ 1, 1, 3, 3}, ArmnnType);
1105  std::vector<float> kernelNoQuantizedValues =
1106  {
1107  1, 2, 3,
1108  4, 5, 6,
1109  7, 8, 9
1110  };
1111 
1112  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
1113  // therefore the output will be 4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
1114  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
1115  std::vector<float> outputExpectedNoQuantizedValues =
1116  {
1117  6., 5., 5., 5.,
1118  6., 5., 5., 5.,
1119  6., 5., 5., 5.,
1120  3., 2., 2., 2.
1121  };
1122 
1123  return Convolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
1124  workloadFactory,
1125  memoryManager,
1126  inputNoQuantizedValues,
1127  inputTensorInfo,
1128  kernelNoQuantizedValues,
1129  kernelTensorInfo,
1130  outputExpectedNoQuantizedValues,
1131  outputTensorInfo,
1132  3,
1133  3,
1134  layout,
1135  biasEnabled);
1136 }

◆ Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest()

LayerTestResult<float, 4> Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::DataLayout  layout 
)

Definition at line 3064 of file Conv2dTestImpl.cpp.

References Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon(), and armnn::Float32.

3068 {
3069  return Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon
3070  <armnn::DataType::Float32, armnn::DataType::Float32>(
3071  workloadFactory, memoryManager, layout, 0.0f, 0);
3072 }
Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon
LayerTestResult< T, 4 > Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTestCommon(armnn::IWorkloadFactory &workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr &memoryManager, const armnn::DataLayout layout, float qScale, int32_t qOffset)
Definition: Conv2dTestImpl.cpp:869

◆ Convolution2dAsymmetricPaddingTest()

LayerTestResult<float, 4> Convolution2dAsymmetricPaddingTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
armnn::DataLayout  layout 
)

Definition at line 3055 of file Conv2dTestImpl.cpp.

3059 {
3060  return SimpleConvolution2dAsymmetricPaddingTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3061  workloadFactory, memoryManager, layout, 0.0f, 0);
3062 }

◆ Convolution2dPerAxisQuantTest()

LayerTestResult<uint8_t, 4> Convolution2dPerAxisQuantTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::DataLayout  layout 
)

Definition at line 3092 of file Conv2dTestImpl.cpp.

References AllocateAndCopyDataToITensorHandle(), CopyDataFromITensorHandle(), CopyDataToITensorHandle(), IWorkloadFactory::CreateConvolution2d(), IWorkloadFactory::CreateTensorHandle(), Convolution2dDescriptor::m_BiasEnabled, Convolution2dDescriptor::m_DataLayout, Convolution2dDescriptor::m_PadBottom, Convolution2dDescriptor::m_PadLeft, Convolution2dDescriptor::m_PadRight, Convolution2dDescriptor::m_PadTop, QueueDescriptorWithParameters< LayerDescriptor >::m_Parameters, Convolution2dDescriptor::m_StrideX, Convolution2dDescriptor::m_StrideY, armnn::NCHW, LayerTestResult< T, n >::output, LayerTestResult< T, n >::outputExpected, and PermuteTensorNhwcToNchw().

3096 {
3097  using namespace armnn;
3098 
3099  const DataType inputType = DataType::QAsymmU8;
3100  const DataType kernelType = DataType::QSymmS8;
3101  const DataType biasType = DataType::Signed32;
3102 
3103  TensorInfo inputInfo ({ 1, 3, 1, 2 }, inputType, 0.5f, 128);
3104  TensorInfo outputInfo({ 1, 3, 1, 3 }, inputType, 1.0f, 128);
3105 
3106  const std::vector<float> quantScales{ 0.5f, 0.75f, 1.0f };
3107  constexpr unsigned int quantDimension = 0;
3108 
3109  TensorInfo kernelInfo({ 3, 1, 1, 2 }, kernelType, quantScales, quantDimension);
3110 
3111  const std::vector<float> biasQuantScales{ 0.25f, 0.375f, 0.5f };
3112  TensorInfo biasInfo({ 3 }, biasType, biasQuantScales, quantDimension);
3113 
3114  std::vector<uint8_t> inputData =
3115  {
3116  138, 108, 138, 108, 138, 108
3117  };
3118 
3119  std::vector<int8_t> kernelData =
3120  {
3121  1, 2, 1, 2, 1, 2
3122  };
3123 
3124  std::vector<int32_t> biasData =
3125  {
3126  4, 4, 4
3127  };
3128 
3129  std::vector<uint8_t> expectedOutputData =
3130  {
3131  121, 118, 115, 121, 118, 115, 121, 118, 115
3132  };
3133 
3134  if (layout == DataLayout::NCHW)
3135  {
3136  PermuteTensorNhwcToNchw(inputInfo, inputData);
3137  PermuteTensorNhwcToNchw(kernelInfo, kernelData);
3138  PermuteTensorNhwcToNchw(outputInfo, expectedOutputData);
3139  }
3140 
3141  Convolution2dDescriptor descriptor;
3142  descriptor.m_StrideX = 1;
3143  descriptor.m_StrideY = 1;
3144  descriptor.m_PadLeft = 0;
3145  descriptor.m_PadRight = 0;
3146  descriptor.m_PadTop = 0;
3147  descriptor.m_PadBottom = 0;
3148  descriptor.m_BiasEnabled = true;
3149  descriptor.m_DataLayout = layout;
3150 
3151  std::unique_ptr<ITensorHandle> inputHandle = workloadFactory.CreateTensorHandle(inputInfo);
3152  std::unique_ptr<ITensorHandle> outputHandle = workloadFactory.CreateTensorHandle(outputInfo);
3153 
3154  WorkloadInfo workloadInfo;
3155  ScopedCpuTensorHandle weightTensor(kernelInfo);
3156  ScopedCpuTensorHandle biasTensor(biasInfo);
3157 
3158  AllocateAndCopyDataToITensorHandle(&weightTensor, kernelData.data());
3159  AllocateAndCopyDataToITensorHandle(&biasTensor, biasData.data());
3160 
3161  Convolution2dQueueDescriptor queueDescriptor;
3162  queueDescriptor.m_Parameters = descriptor;
3163  queueDescriptor.m_Weight = &weightTensor;
3164  queueDescriptor.m_Bias = &biasTensor;
3165 
3166  AddInputToWorkload(queueDescriptor, workloadInfo, inputInfo, inputHandle.get());
3167  AddOutputToWorkload(queueDescriptor, workloadInfo, outputInfo, outputHandle.get());
3168 
3169  std::unique_ptr<IWorkload> workload = workloadFactory.CreateConvolution2d(queueDescriptor, workloadInfo);
3170  inputHandle->Allocate();
3171  outputHandle->Allocate();
3172 
3173  CopyDataToITensorHandle(inputHandle.get(), inputData.data());
3174 
3175  ExecuteWorkload(*workload, memoryManager);
3176 
3177  LayerTestResult<uint8_t, 4> ret(outputInfo);
3178  CopyDataFromITensorHandle(ret.output.origin(), outputHandle.get());
3179  ret.outputExpected = MakeTensor<uint8_t, 4>(outputInfo, expectedOutputData);
3180 
3181  return ret;
3182 }
armnn::Convolution2dDescriptor::m_PadBottom
uint32_t m_PadBottom
Padding bottom value in the height dimension.
Definition: Descriptors.hpp:428
armnn::Convolution2dDescriptor::m_BiasEnabled
bool m_BiasEnabled
Enable/disable bias.
Definition: Descriptors.hpp:438
armnn::Convolution2dDescriptor::m_DataLayout
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
Definition: Descriptors.hpp:440
armnn::Convolution2dDescriptor
A Convolution2dDescriptor for the Convolution2dLayer.
Definition: Descriptors.hpp:392
armnn::Convolution2dDescriptor::m_PadRight
uint32_t m_PadRight
Padding right value in the width dimension.
Definition: Descriptors.hpp:424
armnn
Copyright (c) 2020 ARM Limited.
Definition: 00_introduction.dox:25
armnn::Convolution2dDescriptor::m_PadTop
uint32_t m_PadTop
Padding top value in the height dimension.
Definition: Descriptors.hpp:426
armnn::Convolution2dDescriptor::m_StrideX
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
Definition: Descriptors.hpp:430
armnn::DataType
DataType
Definition: Types.hpp:32
AllocateAndCopyDataToITensorHandle
void AllocateAndCopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:19
CopyDataFromITensorHandle
void CopyDataFromITensorHandle(void *memory, const armnn::ITensorHandle *tensorHandle)
Definition: TensorCopyUtils.cpp:14
armnn::Convolution2dDescriptor::m_StrideY
uint32_t m_StrideY
Stride value when proceeding through input for the height dimension.
Definition: Descriptors.hpp:432
armnn::IWorkloadFactory::CreateTensorHandle
virtual std::unique_ptr< ITensorHandle > CreateTensorHandle(const TensorInfo &tensorInfo, const bool IsMemoryManaged=true) const =0
armnn::WorkloadInfo
Contains information about inputs and outputs to a layer.
Definition: WorkloadInfo.hpp:16
armnn::Convolution2dDescriptor::m_PadLeft
uint32_t m_PadLeft
Padding left value in the width dimension.
Definition: Descriptors.hpp:422
armnn::IWorkloadFactory::CreateConvolution2d
virtual std::unique_ptr< IWorkload > CreateConvolution2d(const Convolution2dQueueDescriptor &descriptor, const WorkloadInfo &info) const
Definition: WorkloadFactory.cpp:1159
CopyDataToITensorHandle
void CopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:9
PermuteTensorNhwcToNchw
void PermuteTensorNhwcToNchw(armnn::TensorInfo &tensorInfo, std::vector< T > &tensorData)
Definition: DataLayoutUtils.hpp:26

◆ DepthwiseConvolution2d2x3x3Dilation3x3Test()

LayerTestResult<T, 4> DepthwiseConvolution2d2x3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2432 of file Conv2dTestImpl.cpp.

2437 {
2438  armnn::TensorInfo inputTensorInfo({1, 2, 10, 10}, ArmnnType);
2439  std::vector<float> inputNoQuantizedValues =
2440  {
2441  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2442  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2443  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2444  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2445  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2446  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2447  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2448  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2449  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2450  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2451 
2452  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2453  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2454  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2455  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2456  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2457  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2458  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2459  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2460  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2461  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2462  };
2463 
2464  armnn::TensorInfo kernelTensorInfo({ 1, 2, 3, 3}, ArmnnType);
2465  std::vector<float> kernelNoQuantizedValues =
2466  {
2467  1, 2, 3,
2468  4, 5, 6,
2469  7, 8, 9,
2470 
2471  1, 2, 3,
2472  4, 5, 6,
2473  7, 8, 9
2474  };
2475 
2476  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
2477  // therefore the output will be 2x4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
2478  armnn::TensorInfo outputTensorInfo({ 1, 2, 4, 4}, ArmnnType);
2479  std::vector<float> outputExpectedNoQuantizedValues =
2480  {
2481  6., 5., 5., 5.,
2482  6., 5., 5., 5.,
2483  6., 5., 5., 5.,
2484  3., 2., 2., 2.,
2485 
2486  6., 5., 5., 5.,
2487  6., 5., 5., 5.,
2488  6., 5., 5., 5.,
2489  3., 2., 2., 2.
2490  };
2491 
2492  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2493  workloadFactory,
2494  memoryManager,
2495  inputNoQuantizedValues,
2496  inputTensorInfo,
2497  kernelNoQuantizedValues,
2498  kernelTensorInfo,
2499  outputExpectedNoQuantizedValues,
2500  outputTensorInfo,
2501  3,
2502  3,
2503  layout,
2504  biasEnabled);
2505 }

◆ DepthwiseConvolution2d3x3Dilation3x3Test()

LayerTestResult<T, 4> DepthwiseConvolution2d3x3Dilation3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2376 of file Conv2dTestImpl.cpp.

2381 {
2382  armnn::TensorInfo inputTensorInfo({1, 1, 10, 10}, ArmnnType);
2383  std::vector<float> inputNoQuantizedValues =
2384  {
2385  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2386  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2387  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2388  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2389  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2390  0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
2391  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2392  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2393  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2394  0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2395  };
2396 
2397  armnn::TensorInfo kernelTensorInfo({ 1, 1, 3, 3}, ArmnnType);
2398  std::vector<float> kernelNoQuantizedValues =
2399  {
2400  1, 2, 3,
2401  4, 5, 6,
2402  7, 8, 9
2403  };
2404 
2405  // Since the dilation rate is 3 this will dilate the kernel to be like 7x7,
2406  // therefore the output will be 4x4: (I−K+2P)/S +1 => (10-7 +0)/1 +1
2407  armnn::TensorInfo outputTensorInfo({ 1, 1, 4, 4}, ArmnnType);
2408  std::vector<float> outputExpectedNoQuantizedValues =
2409  {
2410  6., 5., 5., 5.,
2411  6., 5., 5., 5.,
2412  6., 5., 5., 5.,
2413  3., 2., 2., 2.
2414  };
2415 
2416  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2417  workloadFactory,
2418  memoryManager,
2419  inputNoQuantizedValues,
2420  inputTensorInfo,
2421  kernelNoQuantizedValues,
2422  kernelTensorInfo,
2423  outputExpectedNoQuantizedValues,
2424  outputTensorInfo,
2425  3,
2426  3,
2427  layout,
2428  biasEnabled);
2429 }

◆ DepthwiseConvolution2dAsymmetricTest()

LayerTestResult<float, 4> DepthwiseConvolution2dAsymmetricTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3254 of file Conv2dTestImpl.cpp.

3259 {
3260  return DepthwiseConvolution2dAsymmetricTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3261  workloadFactory, memoryManager, 0.0f, 0, biasEnabled, layout);
3262 }

◆ DepthwiseConvolution2dDepthMul1Int16Test()

LayerTestResult<int16_t, 4> DepthwiseConvolution2dDepthMul1Int16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3306 of file Conv2dTestImpl.cpp.

3311 {
3312  return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3313  workloadFactory, memoryManager, 0.5f, 50, biasEnabled, layout);
3314 }

◆ DepthwiseConvolution2dDepthMul1Test()

LayerTestResult<float, 4> DepthwiseConvolution2dDepthMul1Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3212 of file Conv2dTestImpl.cpp.

3217 {
3218  return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3219  workloadFactory, memoryManager, 0.0f, 0, biasEnabled, layout);
3220 }

◆ DepthwiseConvolution2dDepthMul1Uint8Test()

LayerTestResult<uint8_t, 4> DepthwiseConvolution2dDepthMul1Uint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3274 of file Conv2dTestImpl.cpp.

3279 {
3280  return DepthwiseConvolution2dDepthMul1TestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3281  workloadFactory, memoryManager, 0.5f, 50, biasEnabled, layout);
3282 }

◆ DepthwiseConvolution2dDepthMul64Test()

LayerTestResult<float, 4> DepthwiseConvolution2dDepthMul64Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager 
)

Definition at line 3222 of file Conv2dTestImpl.cpp.

References armnn::Float32, and armnn::NCHW.

3225 {
3226  armnn::TensorInfo inputTensorInfo({ 1, 1, 2, 2 }, armnn::DataType::Float32);
3227  auto input = MakeTensor<float, 4>(inputTensorInfo, { 1.f, 2.f, 3.f, 4.f });
3228 
3229  std::vector<float> kernelData;
3230  std::vector<float> singleDepthKernel{ 1.f, -1.f, -1.f, 1.f };
3231  for (unsigned int i = 0; i < 64; ++i)
3232  {
3233  kernelData.insert(kernelData.end(), singleDepthKernel.begin(), singleDepthKernel.end());
3234  }
3235  armnn::TensorInfo kernelTensorInfo({ 64, 1, 2, 2 }, armnn::DataType::Float32);
3236  auto kernel = MakeTensor<float, 4>(kernelTensorInfo, kernelData);
3237 
3238  std::vector<float> expectedOutputData(64, 0.f);
3239  armnn::TensorInfo outputTensorInfo({ 1, 64, 1, 1 }, armnn::DataType::Float32);
3240  auto expectedOutput = MakeTensor<float, 4>(outputTensorInfo, expectedOutputData);
3241 
3242  return DepthwiseConvolution2dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3243  workloadFactory,
3244  memoryManager,
3245  input,
3246  kernel,
3247  boost::multi_array<float, 1>(),
3248  expectedOutput,
3249  0.f,
3250  0,
3251  armnn::DataLayout::NCHW);
3252 }

◆ DepthwiseConvolution2dDepthNhwcTest()

LayerTestResult<float, 4> DepthwiseConvolution2dDepthNhwcTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled 
)

Definition at line 3203 of file Conv2dTestImpl.cpp.

3207 {
3208  return DepthwiseConvolution2dNhwcTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3209  workloadFactory, memoryManager, 0.0f, 0, biasEnabled);
3210 }

◆ DepthwiseConvolution2dInt16Test()

LayerTestResult<int16_t, 4> DepthwiseConvolution2dInt16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3296 of file Conv2dTestImpl.cpp.

3301 {
3302  return DepthwiseConvolution2dTestImpl<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3303  workloadFactory, memoryManager, 0.5f, 50, biasEnabled, layout);
3304 }

◆ DepthwiseConvolution2dMult2Test()

LayerTestResult<T, 4> DepthwiseConvolution2dMult2Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2600 of file Conv2dTestImpl.cpp.

2605 {
2606  armnn::TensorInfo inputTensorInfo({1, 2, 3, 3}, ArmnnType);
2607  std::vector<float> inputNoQuantizedValues =
2608  {
2609  10.0, 10.0, 10.0,
2610  10.0, 10.0, 10.0,
2611  10.0, 10.0, 10.0,
2612 
2613  21.0, 22.0, 23.0,
2614  24.0, 25.0, 26.0,
2615  27.0, 28.0, 29.0
2616  };
2617 
2618  armnn::TensorInfo kernelTensorInfo({ 2, 2, 2, 2}, ArmnnType);
2619 
2620  std::vector<float> kernelNoQuantizedValues =
2621  {
2622  0.25f, 0.25f,
2623  0.25f, 0.25f,
2624 
2625  0.2f , 0.0f,
2626  0.0f , 0.0f,
2627 
2628  0.0f , 0.0f,
2629  0.0f , 0.1f,
2630 
2631  0.0f , 0.3f,
2632  0.0f , 0.0f
2633 
2634  };
2635 
2636  armnn::TensorInfo outputTensorInfo({ 1, 4, 2, 2}, ArmnnType);
2637  std::vector<float> outputExpectedNoQuantizedValues =
2638  {
2639  10.f, 10.f,
2640  10.f, 10.f,
2641 
2642  1.f, 1.f,
2643  1.f, 1.f,
2644 
2645  4.2000003f, 4.4f,
2646  4.8f, 5.f,
2647 
2648  6.6000004f, 6.9f,
2649  7.5000005f, 7.8f
2650  };
2651 
2652 
2653  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2654  workloadFactory,
2655  memoryManager,
2656  inputNoQuantizedValues,
2657  inputTensorInfo,
2658  kernelNoQuantizedValues,
2659  kernelTensorInfo,
2660  outputExpectedNoQuantizedValues,
2661  outputTensorInfo,
2662  1,
2663  1,
2664  layout,
2665  biasEnabled);
2666 }

◆ DepthwiseConvolution2dMult4Test()

LayerTestResult<T, 4> DepthwiseConvolution2dMult4Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2508 of file Conv2dTestImpl.cpp.

2513 {
2514  armnn::TensorInfo inputTensorInfo({1, 2, 3, 3}, ArmnnType);
2515  std::vector<float> inputNoQuantizedValues =
2516  {
2517  10.0, 10.0, 10.0,
2518  10.0, 10.0, 10.0,
2519  10.0, 10.0, 10.0,
2520 
2521  21.0, 22.0, 23.0,
2522  24.0, 25.0, 26.0,
2523  27.0, 28.0, 29.0
2524  };
2525 
2526  armnn::TensorInfo kernelTensorInfo({ 4, 2, 2, 2}, ArmnnType);
2527 
2528  std::vector<float> kernelNoQuantizedValues =
2529  {
2530  0.25f, 0.25f,
2531  0.25f, 0.25f,
2532 
2533  0.25f, 0.25f,
2534  0.25f, 0.25f,
2535 
2536  0.0f , 0.0f,
2537  0.0f , 0.1f,
2538 
2539  0.0f , 0.0f,
2540  0.0f , 0.1f,
2541 
2542  0.2f , 0.0f,
2543  0.0f , 0.0f,
2544 
2545  0.2f , 0.0f,
2546  0.0f , 0.0f,
2547 
2548  0.0f , 0.3f,
2549  0.0f , 0.0f,
2550 
2551  0.0f , 0.3f,
2552  0.0f , 0.0f
2553  };
2554 
2555  armnn::TensorInfo outputTensorInfo({ 1, 8, 2, 2}, ArmnnType);
2556  std::vector<float> outputExpectedNoQuantizedValues =
2557  {
2558  10.f, 10.f,
2559  10.f, 10.f,
2560 
2561  1.f, 1.f,
2562  1.f, 1.f,
2563 
2564  2.f, 2.f,
2565  2.f, 2.f,
2566 
2567  3.f, 3.f,
2568  3.f, 3.f,
2569 
2570  23.f, 24.f,
2571  26.f, 27.f,
2572 
2573  2.5f, 2.6000001f,
2574  2.8f, 2.9f,
2575 
2576  4.2000003f, 4.4f,
2577  4.8f, 5.f,
2578 
2579  6.6000004f, 6.9f,
2580  7.5000005f, 7.8f
2581  };
2582 
2583 
2584  return DepthwiseConvolution2d3x3DilationTestCommon<ArmnnType, ArmnnBType>(
2585  workloadFactory,
2586  memoryManager,
2587  inputNoQuantizedValues,
2588  inputTensorInfo,
2589  kernelNoQuantizedValues,
2590  kernelTensorInfo,
2591  outputExpectedNoQuantizedValues,
2592  outputTensorInfo,
2593  1,
2594  1,
2595  layout,
2596  biasEnabled);
2597 }

◆ DepthwiseConvolution2dPerAxisQuantTest()

LayerTestResult<uint8_t, 4> DepthwiseConvolution2dPerAxisQuantTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
const armnn::DataLayout  layout 
)

Definition at line 3316 of file Conv2dTestImpl.cpp.

References AllocateAndCopyDataToITensorHandle(), CopyDataFromITensorHandle(), CopyDataToITensorHandle(), IWorkloadFactory::CreateDepthwiseConvolution2d(), IWorkloadFactory::CreateTensorHandle(), DepthwiseConvolution2dDescriptor::m_BiasEnabled, DepthwiseConvolution2dDescriptor::m_DataLayout, DepthwiseConvolution2dDescriptor::m_DilationX, DepthwiseConvolution2dDescriptor::m_DilationY, DepthwiseConvolution2dDescriptor::m_PadBottom, DepthwiseConvolution2dDescriptor::m_PadLeft, DepthwiseConvolution2dDescriptor::m_PadRight, DepthwiseConvolution2dDescriptor::m_PadTop, QueueDescriptorWithParameters< LayerDescriptor >::m_Parameters, DepthwiseConvolution2dDescriptor::m_StrideX, DepthwiseConvolution2dDescriptor::m_StrideY, armnn::NCHW, LayerTestResult< T, n >::output, LayerTestResult< T, n >::outputExpected, and PermuteTensorNhwcToNchw().

3320 {
3321  using namespace armnn;
3322 
3323  const DataType inputType = DataType::QAsymmU8;
3324  const DataType kernelType = DataType::QSymmS8;
3325  const DataType biasType = DataType::Signed32;
3326 
3327  TensorInfo inputInfo ({ 1, 3, 3, 2 }, inputType, 0.5f, 128); // N H W C
3328  TensorInfo outputInfo({ 1, 2, 2, 4 }, inputType, 1.0f, 128); // N H W C
3329 
3330  const std::vector<float> quantScales{ 1.0f, 0.5f, 1.0f, 0.5f };
3331  const unsigned int quantDimension = 0;
3332  TensorInfo kernelInfo({ 2, 2, 2, 2 }, kernelType, quantScales, quantDimension); // M I H W
3333 
3334  const std::vector<float> biasQuantScales{ 0.5f, 0.25f, 0.5f, 0.25f };
3335  constexpr unsigned int biasQuantDimension = 0;
3336  TensorInfo biasInfo({ 4 }, biasType, biasQuantScales, biasQuantDimension);
3337 
3338  std::vector<uint8_t> inputData =
3339  {
3340  129, 130,
3341  129, 130,
3342  129, 130,
3343  129, 130,
3344  129, 130,
3345  129, 130,
3346  129, 130,
3347  129, 130,
3348  129, 130
3349  };
3350 
3351  std::vector<int8_t> kernelData =
3352  {
3353  1, 1, 1, 1,
3354  1, 1, 1, 1,
3355  1, 1, 1, 1,
3356  1, 1, 1, 1
3357  };
3358 
3359  std::vector<int32_t> biasData =
3360  {
3361  4, 4, 4, 4
3362  };
3363 
3364  std::vector<uint8_t> expectedOutputData =
3365  {
3366  132, 130, 134, 131,
3367  132, 130, 134, 131,
3368  132, 130, 134, 131,
3369  132, 130, 134, 131
3370  };
3371 
3372  if (layout == DataLayout::NCHW)
3373  {
3374  PermuteTensorNhwcToNchw(inputInfo, inputData);
3375  PermuteTensorNhwcToNchw(outputInfo, expectedOutputData);
3376  }
3377 
3378  DepthwiseConvolution2dDescriptor descriptor;
3379  descriptor.m_StrideX = 1;
3380  descriptor.m_StrideY = 1;
3381  descriptor.m_PadLeft = 0;
3382  descriptor.m_PadRight = 0;
3383  descriptor.m_PadTop = 0;
3384  descriptor.m_PadBottom = 0;
3385  descriptor.m_DilationX = 1;
3386  descriptor.m_DilationY = 1;
3387  descriptor.m_BiasEnabled = true;
3388  descriptor.m_DataLayout = layout;
3389 
3390  std::unique_ptr<ITensorHandle> inputHandle = workloadFactory.CreateTensorHandle(inputInfo);
3391  std::unique_ptr<ITensorHandle> outputHandle = workloadFactory.CreateTensorHandle(outputInfo);
3392 
3393  WorkloadInfo workloadInfo;
3394  ScopedCpuTensorHandle weightTensor(kernelInfo);
3395  ScopedCpuTensorHandle biasTensor(biasInfo);
3396 
3397  AllocateAndCopyDataToITensorHandle(&weightTensor, kernelData.data());
3398  AllocateAndCopyDataToITensorHandle(&biasTensor, biasData.data());
3399 
3400  DepthwiseConvolution2dQueueDescriptor queueDescriptor;
3401  queueDescriptor.m_Parameters = descriptor;
3402  queueDescriptor.m_Weight = &weightTensor;
3403  queueDescriptor.m_Bias = &biasTensor;
3404 
3405  AddInputToWorkload(queueDescriptor, workloadInfo, inputInfo, inputHandle.get());
3406  AddOutputToWorkload(queueDescriptor, workloadInfo, outputInfo, outputHandle.get());
3407 
3408  std::unique_ptr<IWorkload> workload = workloadFactory.CreateDepthwiseConvolution2d(queueDescriptor, workloadInfo);
3409  inputHandle->Allocate();
3410  outputHandle->Allocate();
3411 
3412  CopyDataToITensorHandle(inputHandle.get(), inputData.data());
3413 
3414  ExecuteWorkload(*workload, memoryManager);
3415 
3416  LayerTestResult<uint8_t, 4> ret(outputInfo);
3417 
3418  CopyDataFromITensorHandle(ret.output.origin(), outputHandle.get());
3419  ret.outputExpected = MakeTensor<uint8_t, 4>(outputInfo, expectedOutputData);
3420 
3421  return ret;
3422 }
armnn::DepthwiseConvolution2dDescriptor::m_BiasEnabled
bool m_BiasEnabled
Enable/disable bias.
Definition: Descriptors.hpp:490
armnn::DepthwiseConvolution2dDescriptor::m_PadBottom
uint32_t m_PadBottom
Padding bottom value in the height dimension.
Definition: Descriptors.hpp:480
armnn::DepthwiseConvolution2dDescriptor::m_DataLayout
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
Definition: Descriptors.hpp:492
armnn::DepthwiseConvolution2dDescriptor::m_PadLeft
uint32_t m_PadLeft
Padding left value in the width dimension.
Definition: Descriptors.hpp:474
armnn
Copyright (c) 2020 ARM Limited.
Definition: 00_introduction.dox:25
armnn::DepthwiseConvolution2dDescriptor::m_DilationY
uint32_t m_DilationY
Dilation factor value for height dimension.
Definition: Descriptors.hpp:488
armnn::DepthwiseConvolution2dDescriptor::m_StrideX
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
Definition: Descriptors.hpp:482
armnn::DataType
DataType
Definition: Types.hpp:32
armnn::DepthwiseConvolution2dDescriptor::m_DilationX
uint32_t m_DilationX
Dilation factor value for width dimension.
Definition: Descriptors.hpp:486
armnn::DepthwiseConvolution2dDescriptor::m_PadTop
uint32_t m_PadTop
Padding top value in the height dimension.
Definition: Descriptors.hpp:478
AllocateAndCopyDataToITensorHandle
void AllocateAndCopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:19
CopyDataFromITensorHandle
void CopyDataFromITensorHandle(void *memory, const armnn::ITensorHandle *tensorHandle)
Definition: TensorCopyUtils.cpp:14
armnn::IWorkloadFactory::CreateTensorHandle
virtual std::unique_ptr< ITensorHandle > CreateTensorHandle(const TensorInfo &tensorInfo, const bool IsMemoryManaged=true) const =0
armnn::DepthwiseConvolution2dDescriptor::m_StrideY
uint32_t m_StrideY
Stride value when proceeding through input for the height dimension.
Definition: Descriptors.hpp:484
armnn::WorkloadInfo
Contains information about inputs and outputs to a layer.
Definition: WorkloadInfo.hpp:16
armnn::IWorkloadFactory::CreateDepthwiseConvolution2d
virtual std::unique_ptr< IWorkload > CreateDepthwiseConvolution2d(const DepthwiseConvolution2dQueueDescriptor &descriptor, const WorkloadInfo &info) const
Definition: WorkloadFactory.cpp:1177
armnn::DepthwiseConvolution2dDescriptor
A DepthwiseConvolution2dDescriptor for the DepthwiseConvolution2dLayer.
Definition: Descriptors.hpp:444
CopyDataToITensorHandle
void CopyDataToITensorHandle(armnn::ITensorHandle *tensorHandle, const void *memory)
Definition: TensorCopyUtils.cpp:9
armnn::DepthwiseConvolution2dDescriptor::m_PadRight
uint32_t m_PadRight
Padding right value in the width dimension.
Definition: Descriptors.hpp:476
PermuteTensorNhwcToNchw
void PermuteTensorNhwcToNchw(armnn::TensorInfo &tensorInfo, std::vector< T > &tensorData)
Definition: DataLayoutUtils.hpp:26

◆ DepthwiseConvolution2dTest()

LayerTestResult<float, 4> DepthwiseConvolution2dTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3193 of file Conv2dTestImpl.cpp.

3198 {
3199  return DepthwiseConvolution2dTestImpl<armnn::DataType::Float32, armnn::DataType::Float32>(
3200  workloadFactory, memoryManager, 0.0f, 0, biasEnabled, layout);
3201 }

◆ DepthwiseConvolution2dUint8Test()

LayerTestResult<uint8_t, 4> DepthwiseConvolution2dUint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3264 of file Conv2dTestImpl.cpp.

3269 {
3270  return DepthwiseConvolution2dTestImpl<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3271  workloadFactory, memoryManager, 0.5f, 50, biasEnabled, layout);
3272 }

◆ SimpleConvolution2d3x3NhwcTest()

LayerTestResult<float, 4> SimpleConvolution2d3x3NhwcTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled 
)

Definition at line 2996 of file Conv2dTestImpl.cpp.

References armnn::NHWC.

3000 {
3001  return SimpleConvolution2d3x3NhwcTestCommon<armnn::DataType::Float32>(
3002  workloadFactory,
3003  memoryManager,
3004  0.f,
3005  0,
3006  biasEnabled,
3007  armnn::DataLayout::NHWC);
3008 }

◆ SimpleConvolution2d3x3QSymm16Test()

LayerTestResult<int16_t, 4> SimpleConvolution2d3x3QSymm16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3045 of file Conv2dTestImpl.cpp.

3050 {
3051  return SimpleConvolution2d3x3TestCommon<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3052  workloadFactory, memoryManager, 0.5f, 50, biasEnabled, layout);
3053 }

◆ SimpleConvolution2d3x3Stride2x2Test()

LayerTestResult<float, 4> SimpleConvolution2d3x3Stride2x2Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3010 of file Conv2dTestImpl.cpp.

3015 {
3016  return SimpleConvolution2d3x3Stride2x2TestCommon<armnn::DataType::Float32>(
3017  workloadFactory,
3018  memoryManager,
3019  0.f,
3020  0,
3021  biasEnabled,
3022  layout);
3023 }

◆ SimpleConvolution2d3x3Test()

LayerTestResult<float, 4> SimpleConvolution2d3x3Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2986 of file Conv2dTestImpl.cpp.

2991 {
2992  return SimpleConvolution2d3x3TestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
2993  workloadFactory, memoryManager, 0.f, 0, biasEnabled, layout);
2994 }

◆ SimpleConvolution2d3x3Uint8Test()

LayerTestResult<uint8_t, 4> SimpleConvolution2d3x3Uint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3025 of file Conv2dTestImpl.cpp.

3030 {
3031  return SimpleConvolution2d3x3TestCommon<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
3032  workloadFactory, memoryManager, 0.5f, 50, biasEnabled, layout);
3033 }

◆ SimpleConvolution2d3x5QSymm16Test()

LayerTestResult<int16_t, 4> SimpleConvolution2d3x5QSymm16Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 3035 of file Conv2dTestImpl.cpp.

3040 {
3041  return SimpleConvolution2d3x5TestCommon<armnn::DataType::QSymmS16, armnn::DataType::Signed32>(
3042  workloadFactory, memoryManager, 0.5f, 50, biasEnabled, layout);
3043 }

◆ SimpleConvolution2d3x5Test()

LayerTestResult<float, 4> SimpleConvolution2d3x5Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2966 of file Conv2dTestImpl.cpp.

2971 {
2972  return SimpleConvolution2d3x5TestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
2973  workloadFactory, memoryManager, 0.f, 0, biasEnabled, layout);
2974 }

◆ SimpleConvolution2d3x5Uint8Test()

LayerTestResult<uint8_t, 4> SimpleConvolution2d3x5Uint8Test ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager,
bool  biasEnabled,
const armnn::DataLayout  layout 
)

Definition at line 2976 of file Conv2dTestImpl.cpp.

2981 {
2982  return SimpleConvolution2d3x5TestCommon<armnn::DataType::QAsymmU8, armnn::DataType::Signed32>(
2983  workloadFactory, memoryManager, 0.5f, 50, biasEnabled, layout);
2984 }

◆ SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTest()

LayerTestResult<float, 4> SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTest ( armnn::IWorkloadFactory &  workloadFactory,
const armnn::IBackendInternal::IMemoryManagerSharedPtr &  memoryManager 
)

Definition at line 3284 of file Conv2dTestImpl.cpp.

3287 {
3288  return SimpleDepthwiseConvolution2d3x3Dilation3x3NhwcTestCommon<armnn::DataType::Float32, armnn::DataType::Float32>(
3289  workloadFactory,
3290  memoryManager,
3291  0.f,
3292  0,
3293  false);
3294 }