From 2b7519dcab1c7907d5c38abceedb078d58998db9 Mon Sep 17 00:00:00 2001
From: Teresa Charlin <teresa.charlinreyes@arm.com>
Date: Tue, 9 Jul 2019 15:45:35 +0100
Subject: IVGCVSW-3468 Add Unit test for Conv2D that combines  strides,
 dilation and padding

Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: Iea99a162e1f0c823cd0f8bc0ae2fb5f461778515
---
 src/backends/reference/test/RefLayerTests.cpp | 32 +++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

(limited to 'src/backends/reference')

diff --git a/src/backends/reference/test/RefLayerTests.cpp b/src/backends/reference/test/RefLayerTests.cpp
index bc64725747..447d95e2ee 100644
--- a/src/backends/reference/test/RefLayerTests.cpp
+++ b/src/backends/reference/test/RefLayerTests.cpp
@@ -121,6 +121,38 @@ ARMNN_AUTO_TEST_CASE(Convolution2d2x3x3Dilation3x3NhwcInt16,
                      false,
                      armnn::DataLayout::NHWC)
 
+ARMNN_AUTO_TEST_CASE(Convolution2d2x2Dilation2x2Padding1x1,
+                     Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test
+                             <armnn::DataType::Float32, armnn::DataType::Float32>,
+                     false,
+                     armnn::DataLayout::NCHW)
+ARMNN_AUTO_TEST_CASE(Convolution2d2x2Dilation2x2Padding1x1TestNhwc,
+                     Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test
+                             <armnn::DataType::Float32, armnn::DataType::Float32>,
+                     false,
+                     armnn::DataLayout::NHWC)
+ARMNN_AUTO_TEST_CASE(Convolution2d2x2Dilation2x2Padding1x1TestUint8,
+                     Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test
+                             <armnn::DataType::QuantisedAsymm8, armnn::DataType::Signed32>,
+                     false,
+                     armnn::DataLayout::NCHW)
+ARMNN_AUTO_TEST_CASE(Convolution2d2x2Dilation2x2Padding1x1TestNhwcUint8,
+                     Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test
+                             <armnn::DataType::QuantisedAsymm8, armnn::DataType::Signed32>,
+                     false,
+                     armnn::DataLayout::NHWC)
+ARMNN_AUTO_TEST_CASE(Convolution2d2x2Dilation2x2Padding1x1TestInt16,
+                     Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test
+                             <armnn::DataType::QuantisedSymm16, armnn::DataType::Signed32>,
+                     false,
+                     armnn::DataLayout::NCHW)
+ARMNN_AUTO_TEST_CASE(Convolution2d2x2Dilation2x2Padding1x1TestNhwcInt16,
+                     Convolution2d2x2Dilation2x2Padding2x2Stride3x3Test
+                             <armnn::DataType::QuantisedSymm16, armnn::DataType::Signed32>,
+                     false,
+                     armnn::DataLayout::NHWC)
+
+
 // Depthwise Convolution
 ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2d, DepthwiseConvolution2dTest, true, armnn::DataLayout::NCHW)
 ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2dUint8, DepthwiseConvolution2dUint8Test, true, armnn::DataLayout::NCHW)
-- 
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