From 92b9f87099260178d2a3d61a42af2a86762eaca7 Mon Sep 17 00:00:00 2001 From: Aron Virginas-Tar Date: Tue, 17 Sep 2019 17:27:04 +0100 Subject: IVGCVSW-3878 Add reference workload for SLICE * Added reference workload implementation and layer tests for all supported tensor dimensions (1d, 2d, 3d, 4d) Signed-off-by: Aron Virginas-Tar Change-Id: I40eb300828933e9183027281105d1a7e597d1569 --- src/backends/reference/workloads/CMakeLists.txt | 4 + .../reference/workloads/RefSliceWorkload.cpp | 29 +++++++ .../reference/workloads/RefSliceWorkload.hpp | 22 +++++ src/backends/reference/workloads/RefWorkloads.hpp | 5 +- src/backends/reference/workloads/Slice.cpp | 95 ++++++++++++++++++++++ src/backends/reference/workloads/Slice.hpp | 21 +++++ 6 files changed, 174 insertions(+), 2 deletions(-) create mode 100644 src/backends/reference/workloads/RefSliceWorkload.cpp create mode 100644 src/backends/reference/workloads/RefSliceWorkload.hpp create mode 100644 src/backends/reference/workloads/Slice.cpp create mode 100644 src/backends/reference/workloads/Slice.hpp (limited to 'src/backends/reference/workloads') diff --git a/src/backends/reference/workloads/CMakeLists.txt b/src/backends/reference/workloads/CMakeLists.txt index 23d6024530..30770956ba 100644 --- a/src/backends/reference/workloads/CMakeLists.txt +++ b/src/backends/reference/workloads/CMakeLists.txt @@ -107,6 +107,8 @@ list(APPEND armnnRefBackendWorkloads_sources RefResizeWorkload.hpp RefRsqrtWorkload.cpp RefRsqrtWorkload.hpp + RefSliceWorkload.cpp + RefSliceWorkload.hpp RefSoftmaxWorkload.cpp RefSoftmaxWorkload.hpp RefSpaceToBatchNdWorkload.cpp @@ -127,6 +129,8 @@ list(APPEND armnnRefBackendWorkloads_sources Resize.hpp Rsqrt.cpp Rsqrt.hpp + Slice.cpp + Slice.hpp Softmax.cpp Softmax.hpp SpaceToBatchNd.hpp diff --git a/src/backends/reference/workloads/RefSliceWorkload.cpp b/src/backends/reference/workloads/RefSliceWorkload.cpp new file mode 100644 index 0000000000..2e448450c1 --- /dev/null +++ b/src/backends/reference/workloads/RefSliceWorkload.cpp @@ -0,0 +1,29 @@ +// +// Copyright © 2019 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "RefSliceWorkload.hpp" + +#include "RefWorkloadUtils.hpp" +#include "Slice.hpp" + +#include + +namespace armnn +{ + +void RefSliceWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefSliceWorkload_Execute"); + + const TensorInfo& inputInfo = GetTensorInfo(m_Data.m_Inputs[0]); + + Slice(inputInfo, + m_Data.m_Parameters, + m_Data.m_Inputs[0]->Map(), + m_Data.m_Outputs[0]->Map(), + GetDataTypeSize(inputInfo.GetDataType())); +} + +} // namespace armnn diff --git a/src/backends/reference/workloads/RefSliceWorkload.hpp b/src/backends/reference/workloads/RefSliceWorkload.hpp new file mode 100644 index 0000000000..006c7b775d --- /dev/null +++ b/src/backends/reference/workloads/RefSliceWorkload.hpp @@ -0,0 +1,22 @@ +// +// Copyright © 2019 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include +#include + +namespace armnn +{ + +class RefSliceWorkload : public BaseWorkload +{ +public: + using BaseWorkload::BaseWorkload; + + virtual void Execute() const override; +}; + +} // namespace armnn diff --git a/src/backends/reference/workloads/RefWorkloads.hpp b/src/backends/reference/workloads/RefWorkloads.hpp index 1ec349ee22..959226adf6 100644 --- a/src/backends/reference/workloads/RefWorkloads.hpp +++ b/src/backends/reference/workloads/RefWorkloads.hpp @@ -41,10 +41,11 @@ #include "RefPadWorkload.hpp" #include "RefPreluWorkload.hpp" #include "RefQuantizeWorkload.hpp" +#include "RefReshapeWorkload.hpp" #include "RefResizeBilinearWorkload.hpp" #include "RefResizeWorkload.hpp" #include "RefRsqrtWorkload.hpp" -#include "RefReshapeWorkload.hpp" +#include "RefSliceWorkload.hpp" #include "RefSplitterWorkload.hpp" #include "RefSoftmaxWorkload.hpp" #include "RefSpaceToBatchNdWorkload.hpp" @@ -56,4 +57,4 @@ #include "Resize.hpp" #include "Softmax.hpp" #include "Splitter.hpp" -#include "TensorBufferArrayView.hpp" \ No newline at end of file +#include "TensorBufferArrayView.hpp" diff --git a/src/backends/reference/workloads/Slice.cpp b/src/backends/reference/workloads/Slice.cpp new file mode 100644 index 0000000000..c7ca3b156e --- /dev/null +++ b/src/backends/reference/workloads/Slice.cpp @@ -0,0 +1,95 @@ +// +// Copyright © 2019 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "Slice.hpp" + +#include +#include +#include + +namespace armnn +{ + +void Slice(const TensorInfo& inputInfo, + const SliceDescriptor& descriptor, + const void* inputData, + void* outputData, + unsigned int dataTypeSize) +{ + const TensorShape& inputShape = inputInfo.GetShape(); + const unsigned int numDims = inputShape.GetNumDimensions(); + + BOOST_ASSERT(descriptor.m_Begin.size() == numDims); + BOOST_ASSERT(descriptor.m_Size.size() == numDims); + + constexpr unsigned int maxNumDims = 4; + BOOST_ASSERT(numDims <= maxNumDims); + + std::vector paddedInput(4); + std::vector paddedBegin(4); + std::vector paddedSize (4); + + const unsigned int numPaddingDims = maxNumDims - numDims; + for (unsigned int i = 0u; i < maxNumDims; ++i) + { + if (i < numPaddingDims) + { + paddedInput[i] = 1u; + paddedBegin[i] = 0u; + paddedSize[i] = 1u; + } + else + { + const unsigned int j = i - numPaddingDims; + paddedInput[i] = inputShape[j]; + paddedBegin[i] = descriptor.m_Begin[j]; + paddedSize[i] = descriptor.m_Size[j]; + } + } + + unsigned int dim0 = paddedInput[0]; + unsigned int dim1 = paddedInput[1]; + unsigned int dim2 = paddedInput[2]; + unsigned int dim3 = paddedInput[3]; + + unsigned int begin0 = paddedBegin[0]; + unsigned int begin1 = paddedBegin[1]; + unsigned int begin2 = paddedBegin[2]; + unsigned int begin3 = paddedBegin[3]; + + unsigned int size0 = paddedSize[0]; + unsigned int size1 = paddedSize[1]; + unsigned int size2 = paddedSize[2]; + unsigned int size3 = paddedSize[3]; + + BOOST_ASSERT(begin0 + size0 <= dim0); + BOOST_ASSERT(begin1 + size1 <= dim1); + BOOST_ASSERT(begin2 + size2 <= dim2); + BOOST_ASSERT(begin3 + size3 <= dim3); + + const unsigned char* input = reinterpret_cast(inputData); + unsigned char* output = reinterpret_cast(outputData); + + boost::ignore_unused(dim0); + for (unsigned int idx0 = begin0; idx0 < begin0 + size0; ++idx0) + { + for (unsigned int idx1 = begin1; idx1 < begin1 + size1; ++idx1) + { + for (unsigned int idx2 = begin2; idx2 < begin2 + size2; ++idx2) + { + for (unsigned int idx3 = begin3; idx3 < begin3 + size3; ++idx3) + { + const unsigned int inputOffset = + (((idx0 * dim1 + idx1) * dim2 + idx2) * dim3 + idx3) * dataTypeSize; + + ::memcpy(output, input + inputOffset, dataTypeSize); + output += dataTypeSize; + } + } + } + } +} + +} // namespace armnn diff --git a/src/backends/reference/workloads/Slice.hpp b/src/backends/reference/workloads/Slice.hpp new file mode 100644 index 0000000000..823f16c052 --- /dev/null +++ b/src/backends/reference/workloads/Slice.hpp @@ -0,0 +1,21 @@ +// +// Copyright © 2019 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include "BaseIterator.hpp" + +#include + +namespace armnn +{ + +void Slice(const TensorInfo& inputInfo, + const SliceDescriptor& descriptor, + const void* inputData, + void* outputData, + unsigned int dataTypeSize); + +} // namespace armnn -- cgit v1.2.1