From 3ea76d5f0d99794cf5f0b60ef3738d0905f10b2a Mon Sep 17 00:00:00 2001 From: Nattapat Chaimanowong Date: Fri, 9 Nov 2018 14:10:38 +0000 Subject: IVGCVSW-2095 Add reference implementation and unit tests for SpaceToBatchNd Change-Id: I27ffebdece6e68460931a44c15b9b029f9fce638 --- src/backends/reference/workloads/CMakeLists.txt | 4 + .../workloads/RefSpaceToBatchNdWorkload.cpp | 34 ++++++ .../workloads/RefSpaceToBatchNdWorkload.hpp | 33 ++++++ src/backends/reference/workloads/RefWorkloads.hpp | 1 + .../reference/workloads/SpaceToBatchNd.cpp | 123 +++++++++++++++++++++ .../reference/workloads/SpaceToBatchNd.hpp | 21 ++++ 6 files changed, 216 insertions(+) create mode 100644 src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp create mode 100644 src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp create mode 100644 src/backends/reference/workloads/SpaceToBatchNd.cpp create mode 100644 src/backends/reference/workloads/SpaceToBatchNd.hpp (limited to 'src/backends/reference/workloads') diff --git a/src/backends/reference/workloads/CMakeLists.txt b/src/backends/reference/workloads/CMakeLists.txt index 7dc72891c7..4cef2d0771 100644 --- a/src/backends/reference/workloads/CMakeLists.txt +++ b/src/backends/reference/workloads/CMakeLists.txt @@ -86,6 +86,8 @@ list(APPEND armnnRefBackendWorkloads_sources RefSoftmaxFloat32Workload.hpp RefSoftmaxUint8Workload.cpp RefSoftmaxUint8Workload.hpp + RefSpaceToBatchNdWorkload.cpp + RefSpaceToBatchNdWorkload.hpp RefSplitterFloat32Workload.cpp RefSplitterFloat32Workload.hpp RefSplitterUint8Workload.cpp @@ -96,6 +98,8 @@ list(APPEND armnnRefBackendWorkloads_sources ResizeBilinear.hpp Softmax.cpp Softmax.hpp + SpaceToBatchNd.hpp + SpaceToBatchNd.cpp Splitter.hpp TensorBufferArrayView.hpp Mean.cpp diff --git a/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp new file mode 100644 index 0000000000..fb98118536 --- /dev/null +++ b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp @@ -0,0 +1,34 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "RefSpaceToBatchNdWorkload.hpp" +#include "SpaceToBatchNd.hpp" + +#include "RefWorkloadUtils.hpp" +#include "TypeUtils.hpp" + +namespace armnn +{ + +template +void RefSpaceToBatchNdWorkload::Execute() const +{ + using T = ResolveType; + + ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, GetName() + "_Execute"); + + const TensorInfo& inputInfo = GetTensorInfo(m_Data.m_Inputs[0]); + const TensorInfo& outputInfo = GetTensorInfo(m_Data.m_Outputs[0]); + + const T* inputData = GetInputTensorData(0, m_Data); + T* outputData = GetOutputTensorData(0, m_Data); + + SpaceToBatchNd(inputInfo, outputInfo, m_Data.m_Parameters, inputData, outputData); +} + +template class RefSpaceToBatchNdWorkload; +template class RefSpaceToBatchNdWorkload; + +} //namespace armnn diff --git a/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp new file mode 100644 index 0000000000..3a08662ff7 --- /dev/null +++ b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp @@ -0,0 +1,33 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// +#pragma once + +#include "backendsCommon/Workload.hpp" + +#include + +namespace armnn +{ + +template +class RefSpaceToBatchNdWorkload : public TypedWorkload +{ +public: + static const std::string& GetName() + { + static const std::string name = std::string("RefSpaceToBatchNd") + GetDataTypeName(DataType) + "Workload"; + return name; + } + + using TypedWorkload::m_Data; + using TypedWorkload::TypedWorkload; + + void Execute() const override; +}; + +using RefSpaceToBatchNdFloat32Workload = RefSpaceToBatchNdWorkload; +using RefSpaceToBatchNdUint8Workload = RefSpaceToBatchNdWorkload; + +} //namespace armnn diff --git a/src/backends/reference/workloads/RefWorkloads.hpp b/src/backends/reference/workloads/RefWorkloads.hpp index 14e6699a73..03907a6b91 100644 --- a/src/backends/reference/workloads/RefWorkloads.hpp +++ b/src/backends/reference/workloads/RefWorkloads.hpp @@ -41,6 +41,7 @@ #include "BatchNormImpl.hpp" #include "Activation.hpp" #include "Merger.hpp" +#include "RefSpaceToBatchNdWorkload.hpp" #include "RefSplitterFloat32Workload.hpp" #include "RefConstantFloat32Workload.hpp" #include "RefActivationFloat32Workload.hpp" diff --git a/src/backends/reference/workloads/SpaceToBatchNd.cpp b/src/backends/reference/workloads/SpaceToBatchNd.cpp new file mode 100644 index 0000000000..48c212764f --- /dev/null +++ b/src/backends/reference/workloads/SpaceToBatchNd.cpp @@ -0,0 +1,123 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "SpaceToBatchNd.hpp" + +namespace armnn +{ + +unsigned int GetOffset(const TensorShape& shape, + unsigned int b, + unsigned int h, + unsigned int w, + unsigned int c, + const DataLayoutIndexed& dataLayout) +{ + if (dataLayout.GetDataLayout() == DataLayout::NHWC) + { + return ((b * shape[dataLayout.GetHeightIndex()] + h) * shape[dataLayout.GetWidthIndex()] + w) * + shape[dataLayout.GetChannelsIndex()] + c; + } + else + { + return ((b * shape[dataLayout.GetChannelsIndex()] + c) * shape[dataLayout.GetHeightIndex()] + h) * + shape[dataLayout.GetWidthIndex()] + w; + } +} + +template +void SpaceToBatchNd(const TensorInfo& inputInfo, + const TensorInfo& outputInfo, + const SpaceToBatchNdDescriptor& params, + const T* inputData, + T* outputData) +{ + DataLayoutIndexed dataLayout = params.m_DataLayout; + + const TensorShape& inputShape = inputInfo.GetShape(); + const TensorShape& outputShape = outputInfo.GetShape(); + + const unsigned int channels = inputShape[dataLayout.GetChannelsIndex()]; + + const unsigned int inputBatchSize = inputShape[0]; + const unsigned int inputHeight = inputShape[dataLayout.GetHeightIndex()]; + const unsigned int inputWidth = inputShape[dataLayout.GetWidthIndex()]; + + const unsigned int outputBatchSize = outputShape[0]; + const unsigned int outputHeight = outputShape[dataLayout.GetHeightIndex()]; + const unsigned int outputWidth = outputShape[dataLayout.GetWidthIndex()]; + + const unsigned int blockHeight = params.m_BlockShape[0]; + const unsigned int blockWidth = params.m_BlockShape[1]; + + const unsigned int paddingTop = params.m_PadList[0].first; + const unsigned int paddingLeft = params.m_PadList[1].first; + + for (unsigned int outB = 0; outB < outputBatchSize; outB++) + { + unsigned int inB = outB % inputBatchSize; + + unsigned int shiftW = (outB / inputBatchSize) % blockWidth; + unsigned int shiftH = (outB / inputBatchSize) / blockWidth; + + for (unsigned int outH = 0; outH < outputHeight; outH++) + { + for (unsigned int outW = 0; outW < outputWidth; outW++) + { + if (outH * blockHeight + shiftH < paddingTop || + outH * blockHeight + shiftH >= paddingTop + inputHeight || + outW * blockWidth + shiftW < paddingLeft || + outW * blockWidth + shiftW >= paddingLeft + inputWidth) + { + for (unsigned int c = 0; c < channels; c++) + { + unsigned int outOffset = GetOffset(outputShape, + outB, + outH, + outW, + c, + dataLayout); + outputData[outOffset] = 0; + } + } + else + { + for (unsigned int c = 0; c < channels; c++) + { + unsigned int inOffset = GetOffset(inputShape, + inB, + (outH * blockHeight + shiftH) - paddingTop, + (outW * blockWidth + shiftW) - paddingLeft, + c, + dataLayout); + + unsigned int outOffset = GetOffset(outputShape, + outB, + outH, + outW, + c, + dataLayout); + + outputData[outOffset] = inputData[inOffset]; + } + } + } + } + } +} + +template void SpaceToBatchNd(const TensorInfo& inputInfo, + const TensorInfo& outputInfo, + const SpaceToBatchNdDescriptor& params, + const float* inputData, + float* outData); + +template void SpaceToBatchNd(const TensorInfo& inputInfo, + const TensorInfo& outputInfo, + const SpaceToBatchNdDescriptor& params, + const uint8_t* inputData, + uint8_t* outData); + +} //namespace armnn diff --git a/src/backends/reference/workloads/SpaceToBatchNd.hpp b/src/backends/reference/workloads/SpaceToBatchNd.hpp new file mode 100644 index 0000000000..e74e457a72 --- /dev/null +++ b/src/backends/reference/workloads/SpaceToBatchNd.hpp @@ -0,0 +1,21 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include +#include "armnn/Tensor.hpp" + +namespace armnn +{ + +template +void SpaceToBatchNd(const TensorInfo& inputInfo, + const TensorInfo& outputInfo, + const SpaceToBatchNdDescriptor& params, + const T* inputData, + T* outputData); + +} //namespace armnn -- cgit v1.2.1