From 988354de127528bdebb98fd25661fbf2f39f17dd Mon Sep 17 00:00:00 2001
From: Tianle Cheng <tianle.cheng@arm.com>
Date: Wed, 28 Jun 2023 13:20:47 +0100
Subject: IVGCVSW-7831: Front end and Reference Implementation for REVERSE_V2

 * Descriptors added for ReverseV2
 * Layer definition added
 * Input validation added
 * Reference workload implementation for ReverseV2 added
 * Reference layer unit tests made for ReverseV2
 * CompareTensors method updated to support comparison between empty tensors
 * CMake and other build files updated

Signed-off-by: Tianle Cheng <tianle.cheng@arm.com>
Change-Id: I805738454421309fda77c44218a8df171d68dc18
---
 src/backends/reference/workloads/ReverseV2Impl.hpp | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 src/backends/reference/workloads/ReverseV2Impl.hpp

(limited to 'src/backends/reference/workloads/ReverseV2Impl.hpp')

diff --git a/src/backends/reference/workloads/ReverseV2Impl.hpp b/src/backends/reference/workloads/ReverseV2Impl.hpp
new file mode 100644
index 0000000000..bc1fe1d432
--- /dev/null
+++ b/src/backends/reference/workloads/ReverseV2Impl.hpp
@@ -0,0 +1,21 @@
+//
+// Copyright © 2023 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include "Encoders.hpp"
+#include "Decoders.hpp"
+
+#include <armnn/backends/WorkloadData.hpp>
+
+namespace armnn
+{
+
+void ReverseV2(const ReverseV2Descriptor& params,
+               const TensorInfo& inputInfo,
+               Decoder<float>& inputDecoder,
+               Encoder<float>& outputEncoder);
+
+} // namespace armnn
\ No newline at end of file
-- 
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