From 1e4c31dafb1c8984a126fa1d211ed8f9eedaf7cc Mon Sep 17 00:00:00 2001 From: narpra01 Date: Fri, 28 Sep 2018 11:07:51 +0100 Subject: IVGCVSW-1812 Adding Ref implementation and tests of MeanWorkloads Change-Id: I6fb15c407024e3b91d5abf4513f8090be5821760 --- .../reference/workloads/RefMeanFloat32Workload.cpp | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 src/backends/reference/workloads/RefMeanFloat32Workload.cpp (limited to 'src/backends/reference/workloads/RefMeanFloat32Workload.cpp') diff --git a/src/backends/reference/workloads/RefMeanFloat32Workload.cpp b/src/backends/reference/workloads/RefMeanFloat32Workload.cpp new file mode 100644 index 0000000000..a23906b8aa --- /dev/null +++ b/src/backends/reference/workloads/RefMeanFloat32Workload.cpp @@ -0,0 +1,35 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "RefMeanFloat32Workload.hpp" + +#include "Mean.hpp" +#include "RefWorkloadUtils.hpp" + +#include "Profiling.hpp" +#include "vector" + +namespace armnn +{ + +RefMeanFloat32Workload::RefMeanFloat32Workload(const MeanQueueDescriptor& descriptor, const WorkloadInfo& info) + :Float32Workload(descriptor, info) {} + + +void RefMeanFloat32Workload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefMeanFloat32Workload_Execute"); + + const TensorInfo& inputInfo = GetTensorInfo(m_Data.m_Inputs[0]); + const TensorInfo& outputInfo = GetTensorInfo(m_Data.m_Outputs[0]); + const float* inputData = GetInputTensorDataFloat(0, m_Data); + float* outputData = GetOutputTensorDataFloat(0, m_Data); + + Mean(inputInfo, outputInfo, m_Data.m_Parameters.m_Axis, inputData, outputData); +} + +} //namespace armnn + + -- cgit v1.2.1