From bc67cef3e3dc9e7fe9c4331495009eda48c89527 Mon Sep 17 00:00:00 2001 From: Narumol Prangnawarat Date: Thu, 31 Jan 2019 15:31:54 +0000 Subject: IVGCVSW-2557 Ref Workload Implementation for Detection PostProcess * implementation of DetectionPostProcessQueueDescriptor validate * add Uint8ToFloat32Workload * add implementation of Detection PostProcess functionalities * add ref workload implemenentation for float and uint8 * add layer support for Detection PostProcess in ref * unit tests Change-Id: I650461f49edbb3c533d68ef8700377af51bc3592 --- .../reference/workloads/DetectionPostProcess.hpp | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 src/backends/reference/workloads/DetectionPostProcess.hpp (limited to 'src/backends/reference/workloads/DetectionPostProcess.hpp') diff --git a/src/backends/reference/workloads/DetectionPostProcess.hpp b/src/backends/reference/workloads/DetectionPostProcess.hpp new file mode 100644 index 0000000000..06e9e15781 --- /dev/null +++ b/src/backends/reference/workloads/DetectionPostProcess.hpp @@ -0,0 +1,29 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// +#pragma once + +#include "armnn/Tensor.hpp" +#include "armnn/Descriptors.hpp" + +namespace armnn +{ + +void DetectionPostProcess(const TensorInfo& boxEncodingsInfo, + const TensorInfo& scoresInfo, + const TensorInfo& anchorsInfo, + const TensorInfo& detectionBoxesInfo, + const TensorInfo& detectionClassesInfo, + const TensorInfo& detectionScoresInfo, + const TensorInfo& numDetectionsInfo, + const DetectionPostProcessDescriptor& desc, + const float* boxEncodings, + const float* scores, + const float* anchors, + float* detectionBoxes, + float* detectionClasses, + float* detectionScores, + float* numDetections); + +} // namespace armnn -- cgit v1.2.1