From 42666a17df1a36bb4f6f24866be73da0e55de020 Mon Sep 17 00:00:00 2001 From: Matteo Martincigh Date: Wed, 29 May 2019 08:53:41 +0100 Subject: IVGCVSW-3171 Extend the Strided Slice Ref workload to support the QSymm16 * Added support for QSymm16 in the Strided Slice workload * Added unit tests Change-Id: I84485bc2fd5ad2b4edb49c644b644878e0e5aded Signed-off-by: Matteo Martincigh --- src/backends/reference/test/RefLayerTests.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/backends/reference/test/RefLayerTests.cpp') diff --git a/src/backends/reference/test/RefLayerTests.cpp b/src/backends/reference/test/RefLayerTests.cpp index 690a78c21c..d3a597586b 100644 --- a/src/backends/reference/test/RefLayerTests.cpp +++ b/src/backends/reference/test/RefLayerTests.cpp @@ -571,6 +571,16 @@ ARMNN_AUTO_TEST_CASE(StridedSlice3DReverseUint8, StridedSlice3DReverseUint8Test) ARMNN_AUTO_TEST_CASE(StridedSlice2DUint8, StridedSlice2DUint8Test) ARMNN_AUTO_TEST_CASE(StridedSlice2DReverseUint8, StridedSlice2DReverseUint8Test) +ARMNN_AUTO_TEST_CASE(StridedSlice4DInt16, StridedSlice4DInt16Test) +ARMNN_AUTO_TEST_CASE(StridedSlice4DReverseInt16, StridedSlice4DReverseInt16Test) +ARMNN_AUTO_TEST_CASE(StridedSliceSimpleStrideInt16, StridedSliceSimpleStrideInt16Test) +ARMNN_AUTO_TEST_CASE(StridedSliceSimpleRangeMaskInt16, StridedSliceSimpleRangeMaskInt16Test) +ARMNN_AUTO_TEST_CASE(StridedSliceShrinkAxisMaskInt16, StridedSliceShrinkAxisMaskInt16Test) +ARMNN_AUTO_TEST_CASE(StridedSlice3DInt16, StridedSlice3DInt16Test) +ARMNN_AUTO_TEST_CASE(StridedSlice3DReverseInt16, StridedSlice3DReverseInt16Test) +ARMNN_AUTO_TEST_CASE(StridedSlice2DInt16, StridedSlice2DInt16Test) +ARMNN_AUTO_TEST_CASE(StridedSlice2DReverseInt16, StridedSlice2DReverseInt16Test) + // Debug ARMNN_AUTO_TEST_CASE(Debug4DFloat32, Debug4DFloat32Test) ARMNN_AUTO_TEST_CASE(Debug3DFloat32, Debug3DFloat32Test) -- cgit v1.2.1