From 615ad6cde5a56d8f38e1b9261621b40671a00ed7 Mon Sep 17 00:00:00 2001 From: Teresa Charlin Date: Tue, 26 Oct 2021 12:22:20 +0100 Subject: IVGCVSW-6169 Add GpuAcc Conv3d Workload Signed-off-by: Teresa Charlin Change-Id: I8b73dccc14ef71cc083896102e24afb2e56e72e2 --- src/backends/cl/workloads/CMakeLists.txt | 2 + .../cl/workloads/ClConvolution3dWorkload.cpp | 116 +++++++++++++++++++++ .../cl/workloads/ClConvolution3dWorkload.hpp | 41 ++++++++ src/backends/cl/workloads/ClWorkloads.hpp | 1 + 4 files changed, 160 insertions(+) create mode 100644 src/backends/cl/workloads/ClConvolution3dWorkload.cpp create mode 100644 src/backends/cl/workloads/ClConvolution3dWorkload.hpp (limited to 'src/backends/cl/workloads') diff --git a/src/backends/cl/workloads/CMakeLists.txt b/src/backends/cl/workloads/CMakeLists.txt index 93ae678f98..6e7dd36f47 100644 --- a/src/backends/cl/workloads/CMakeLists.txt +++ b/src/backends/cl/workloads/CMakeLists.txt @@ -32,6 +32,8 @@ list(APPEND armnnClBackendWorkloads_sources ClConvertFp32ToFp16Workload.hpp ClConvolution2dWorkload.cpp ClConvolution2dWorkload.hpp + ClConvolution3dWorkload.cpp + ClConvolution3dWorkload.hpp ClDepthToSpaceWorkload.cpp ClDepthToSpaceWorkload.hpp ClDepthwiseConvolutionWorkload.cpp diff --git a/src/backends/cl/workloads/ClConvolution3dWorkload.cpp b/src/backends/cl/workloads/ClConvolution3dWorkload.cpp new file mode 100644 index 0000000000..18a2c31b51 --- /dev/null +++ b/src/backends/cl/workloads/ClConvolution3dWorkload.cpp @@ -0,0 +1,116 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ClConvolution3dWorkload.hpp" + +#include "ClWorkloadUtils.hpp" + +#include +#include +#include +#include +#include +#include + +#include + +namespace armnn +{ +using namespace armcomputetensorutils; + +arm_compute::Status ClConvolution3dWorkloadValidate(const TensorInfo& input, + const TensorInfo& output, + const Convolution3dDescriptor& descriptor, + const TensorInfo& weights, + const Optional& biases, + bool isFastMathEnabled, + const ActivationDescriptor* activationDescriptor) +{ + const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout); + const arm_compute::TensorInfo aclWeightsInfo = BuildArmComputeTensorInfo(weights, descriptor.m_DataLayout); + + arm_compute::TensorInfo aclBiasesInfo; + arm_compute::TensorInfo* optionalAclBiasesInfo = nullptr; + if (descriptor.m_BiasEnabled) + { + ARMNN_ASSERT(biases.has_value()); + aclBiasesInfo = BuildArmComputeTensorInfo(biases.value(), descriptor.m_DataLayout); + optionalAclBiasesInfo = &aclBiasesInfo; + } + + const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, descriptor.m_DataLayout); + + const arm_compute::Conv3dInfo aclConv3DInfo = ComputeConv3DInfo(descriptor, + isFastMathEnabled, + activationDescriptor); + + return arm_compute::CLConv3D::validate(&aclInputInfo, + &aclWeightsInfo, + optionalAclBiasesInfo, + &aclOutputInfo, + aclConv3DInfo); +} + +ClConvolution3dWorkload::ClConvolution3dWorkload(const Convolution3dQueueDescriptor& descriptor, + const WorkloadInfo& info, + std::shared_ptr& memoryManager, + const arm_compute::CLCompileContext& clCompileContext, + const bool isFastMathEnabled) + : BaseWorkload(descriptor, info) + , m_ConvolutionLayer() +{ + IgnoreUnused(memoryManager); + + uint32_t numInputs = m_Data.m_Parameters.m_BiasEnabled ? 3: 2; + m_Data.ValidateInputsOutputs("ClConvolution3dWorkload", numInputs, 1); + + arm_compute::ICLTensor& input = static_cast(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& weights = static_cast(m_Data.m_Inputs[1])->GetTensor(); + arm_compute::ICLTensor* biasesPtr = nullptr; + if (m_Data.m_Parameters.m_BiasEnabled) + { + biasesPtr = &static_cast(m_Data.m_Inputs[2])->GetTensor(); + } + arm_compute::ICLTensor& output = static_cast(m_Data.m_Outputs[0])->GetTensor(); + + arm_compute::DataLayout aclDataLayout = ConvertDataLayout(m_Data.m_Parameters.m_DataLayout); + input.info()->set_data_layout(aclDataLayout); + weights.info()->set_data_layout(aclDataLayout); + output.info()->set_data_layout(aclDataLayout); + + const arm_compute::Conv3dInfo aclConv3DInfo = ComputeConv3DInfo(descriptor, + isFastMathEnabled); + + m_ConvolutionLayer.configure(clCompileContext, + &input, + &weights, + biasesPtr, + &output, + aclConv3DInfo); + + // Add details for profiling output + WorkloadInfo detailsInfo; + + detailsInfo.m_InputTensorInfos = info.m_InputTensorInfos; + detailsInfo.m_OutputTensorInfos = info.m_OutputTensorInfos; + + // Report Profiling Details + ARMNN_REPORT_PROFILING_WORKLOAD_DESC("ClConvolution3dWorkload_Construct", + descriptor.m_Parameters, + detailsInfo, + this->GetGuid()); + + // Force Compute Library to perform the necessary copying and reshaping, after which + // delete all the input tensors that will no longer be needed + m_ConvolutionLayer.prepare(); +} + +void ClConvolution3dWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL_GUID("ClConvolution3dWorkload_Execute", this->GetGuid()); + RunClFunction(m_ConvolutionLayer, CHECK_LOCATION()); +} + +} //namespace armnn diff --git a/src/backends/cl/workloads/ClConvolution3dWorkload.hpp b/src/backends/cl/workloads/ClConvolution3dWorkload.hpp new file mode 100644 index 0000000000..93654ecad8 --- /dev/null +++ b/src/backends/cl/workloads/ClConvolution3dWorkload.hpp @@ -0,0 +1,41 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include + +#include +#include + +#include + +namespace armnn +{ + +arm_compute::Status ClConvolution3dWorkloadValidate(const TensorInfo& input, + const TensorInfo& output, + const Convolution3dDescriptor& descriptor, + const TensorInfo& weights, + const Optional& biases, + bool isFastMathEnabled = false, + const ActivationDescriptor* activationDescriptor = nullptr); + +class ClConvolution3dWorkload : public BaseWorkload +{ +public: + ClConvolution3dWorkload(const Convolution3dQueueDescriptor& descriptor, + const WorkloadInfo& info, + std::shared_ptr& memoryManager, + const arm_compute::CLCompileContext& clCompileContext, + const bool isFastMathEnabled = false); + void Execute() const override; + +private: + mutable arm_compute::CLConv3D m_ConvolutionLayer; +}; + +} //namespace armnn + diff --git a/src/backends/cl/workloads/ClWorkloads.hpp b/src/backends/cl/workloads/ClWorkloads.hpp index 3e0984eddf..bb04b17d32 100644 --- a/src/backends/cl/workloads/ClWorkloads.hpp +++ b/src/backends/cl/workloads/ClWorkloads.hpp @@ -15,6 +15,7 @@ #include "ClCastWorkload.hpp" #include "ClChannelShuffleWorkload.hpp" #include "ClConvolution2dWorkload.hpp" +#include "ClConvolution3dWorkload.hpp" #include "ClDepthToSpaceWorkload.hpp" #include "ClDepthwiseConvolutionWorkload.hpp" #include "ClDequantizeWorkload.hpp" -- cgit v1.2.1