From 34c1c38944b47b881febdfb9f98103dbdc949ed0 Mon Sep 17 00:00:00 2001 From: John Mcloughlin Date: Wed, 17 May 2023 15:08:36 +0100 Subject: IVGCVSW-7400 POW IVGCVSW-7278 SQUARED_DIFFERENCE to CpuAcc and GpuAcc * Add POW SQUARED_DIFFERENCE and Unit tests for CpuAcc and GpuAcc Signed-off-by: John Mcloughlin Signed-off-by: Teresa Charlin Change-Id: Ifa78af2a2fda2074586d8e4d9a506b1b13fa5755 --- .../cl/workloads/ClElementwiseBinaryWorkload.hpp | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 src/backends/cl/workloads/ClElementwiseBinaryWorkload.hpp (limited to 'src/backends/cl/workloads/ClElementwiseBinaryWorkload.hpp') diff --git a/src/backends/cl/workloads/ClElementwiseBinaryWorkload.hpp b/src/backends/cl/workloads/ClElementwiseBinaryWorkload.hpp new file mode 100644 index 0000000000..addd6e6085 --- /dev/null +++ b/src/backends/cl/workloads/ClElementwiseBinaryWorkload.hpp @@ -0,0 +1,34 @@ +// +// Copyright © 2023 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include "ClBaseWorkload.hpp" + +#include + +namespace armnn +{ + +class ClElementwiseBinaryWorkload : public ClBaseWorkload +{ +public: + ClElementwiseBinaryWorkload(const ElementwiseBinaryQueueDescriptor& descriptor, + const WorkloadInfo& info, + const arm_compute::CLCompileContext& clCompileContext); + + void Execute() const override; + +private: + std::unique_ptr m_ElementwiseBinaryLayer; + +}; + +arm_compute::Status ClElementwiseBinaryValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output, + const ElementwiseBinaryDescriptor& descriptor, + const ActivationDescriptor* activationDescriptor = nullptr); +} //namespace armnn \ No newline at end of file -- cgit v1.2.1