From f77cab57b3eca1425384d4d5bfe44d76fc7023b9 Mon Sep 17 00:00:00 2001 From: Teresa Charlin Date: Thu, 1 Jun 2023 16:15:13 +0100 Subject: IVGCVSW-7785 Extend support for 3D tensors BATCH_TO_SPACE and SPACE_TO_BATCH in CpuRef * Both layers were assuming 4D tensors, now 3D is supported too. * Remove some unnecessary includes * Add Unit Tests Signed-off-by: Teresa Charlin Change-Id: I7bdd11e4936a27cd97ec65fd915e6ccaa1494cff --- src/backends/backendsCommon/WorkloadData.cpp | 105 +++++++++++++----- .../test/layerTests/BatchToSpaceNdTestImpl.hpp | 27 +++++ .../test/layerTests/SpaceToBatchNdTestImpl.cpp | 121 +++++++++++++++++++++ .../test/layerTests/SpaceToBatchNdTestImpl.hpp | 15 +++ 4 files changed, 243 insertions(+), 25 deletions(-) (limited to 'src/backends/backendsCommon') diff --git a/src/backends/backendsCommon/WorkloadData.cpp b/src/backends/backendsCommon/WorkloadData.cpp index 6a5963ddcb..d4ae08d874 100644 --- a/src/backends/backendsCommon/WorkloadData.cpp +++ b/src/backends/backendsCommon/WorkloadData.cpp @@ -1815,47 +1815,66 @@ void SpaceToBatchNdQueueDescriptor::Validate(const WorkloadInfo& workloadInfo) c const TensorInfo& inputTensorInfo = workloadInfo.m_InputTensorInfos[0]; const TensorInfo& outputTensorInfo = workloadInfo.m_OutputTensorInfos[0]; - ValidateTensorNumDimensions(inputTensorInfo, descriptorName, 4, "input"); - ValidateTensorNumDimensions(outputTensorInfo, descriptorName, 4, "output"); - - if (m_Parameters.m_BlockShape.size() != 2) - { - throw InvalidArgumentException(descriptorName + ": Block Shape must contain 2 spatial dimensions."); - } - if (m_Parameters.m_BlockShape.size() != m_Parameters.m_PadList.size()) { throw InvalidArgumentException(descriptorName + ": Pad List must contain the same number of " "dimensions as Block Shape."); } - const TensorShape& inputShape = inputTensorInfo.GetShape(); - - std::pair heightPad = m_Parameters.m_PadList[0]; - std::pair widthPad = m_Parameters.m_PadList[1]; + if (m_Parameters.m_BlockShape.size() == 2) + { + ValidateTensorNumDimensions(inputTensorInfo, descriptorName, 4, "input"); + ValidateTensorNumDimensions(outputTensorInfo, descriptorName, 4, "output"); + } + else if (m_Parameters.m_BlockShape.size() == 1) + { + ValidateTensorNumDimensions(inputTensorInfo, descriptorName, 3, "input"); + ValidateTensorNumDimensions(outputTensorInfo, descriptorName, 3, "output"); + } + else + { + throw InvalidArgumentException(descriptorName + ": Invalid Block and Crops size."); + } + // Check input + padding and output have the same number of elements DataLayoutIndexed dimensionIndices(m_Parameters.m_DataLayout); + const unsigned int inputHeight = inputTensorInfo.GetShape()[dimensionIndices.GetHeightIndex()] + + m_Parameters.m_PadList[0].first + m_Parameters.m_PadList[0].second; + const unsigned int inputWidth = (inputTensorInfo.GetNumDimensions() == 3) ? 1 : + inputTensorInfo.GetShape()[dimensionIndices.GetWidthIndex()] + + m_Parameters.m_PadList[1].first + m_Parameters.m_PadList[1].second; - const unsigned int inputWidth = inputShape[dimensionIndices.GetWidthIndex()] + - widthPad.first + widthPad.second; - const unsigned int inputHeight = inputShape[dimensionIndices.GetHeightIndex()] + - heightPad.first + heightPad.second; + const int channelsIndex_int = (m_Parameters.m_DataLayout == DataLayout::NCHW) ? 1 : -1; + const unsigned int channelsIndex = channelsIndex_int < 0 ? + static_cast(channelsIndex_int) + inputTensorInfo.GetNumDimensions() + : static_cast(channelsIndex_int); - const unsigned int numInputElements = inputShape[0] * inputHeight * inputWidth * - inputShape[dimensionIndices.GetChannelsIndex()]; - const unsigned int numOutputElements = outputTensorInfo.GetNumElements(); + const unsigned int numInputElements = inputTensorInfo.GetShape()[0] * + inputHeight * + inputWidth * + inputTensorInfo.GetShape()[channelsIndex]; - if (numOutputElements != numInputElements) + if (outputTensorInfo.GetNumElements() != numInputElements) { throw InvalidArgumentException(descriptorName + ": Input tensor has " + - to_string(numInputElements) + " after padding but output tensor has " + - to_string(numOutputElements) + " elements."); + to_string(numInputElements) + " after padding but output tensor has " + + to_string(outputTensorInfo.GetNumElements()) + " elements."); } - if (inputHeight % m_Parameters.m_BlockShape[0] != 0 || inputWidth % m_Parameters.m_BlockShape[1] != 0) + // In a 4D tensor, there will be 2 spatialDimensions (H and W), and the for loop will run twice. + // In a 3D tensor, there will be 1 spatialDimensions, and the for loop will run once. + unsigned int firstSpatialDimension = m_Parameters.m_DataLayout == DataLayout::NCHW ? 2 : 1; + for (unsigned int i = 0; i < m_Parameters.m_BlockShape.size(); ++i) { - throw InvalidArgumentException(descriptorName + ": Input shape after padding must be " - "divisible by Block Shape in all spatial dimensions"); + unsigned int spatialDimension = firstSpatialDimension + i; + auto inputSize = inputTensorInfo.GetShape()[spatialDimension] + + m_Parameters.m_PadList[i].first + + m_Parameters.m_PadList[i].second; + if (inputSize % m_Parameters.m_BlockShape[i] != 0) + { + throw InvalidArgumentException(descriptorName + ": Input dimension size after padding must be " + "divisible by Block Shape in dimension: " + to_string(spatialDimension) + "."); + } } std::vector supportedTypes = @@ -2472,6 +2491,42 @@ void BatchToSpaceNdQueueDescriptor::Validate(const WorkloadInfo& workloadInfo) c const TensorInfo& inputTensorInfo = workloadInfo.m_InputTensorInfos[0]; const TensorInfo& outputTensorInfo = workloadInfo.m_OutputTensorInfos[0]; + if (m_Parameters.m_BlockShape.size() != m_Parameters.m_Crops.size()) + { + throw InvalidArgumentException(descriptorName + ": Crops must contain the same number of " + "dimensions as Block Shape."); + } + + if (m_Parameters.m_BlockShape.size() == 2) + { + ValidateTensorNumDimensions(inputTensorInfo, descriptorName, 4, "input"); + ValidateTensorNumDimensions(outputTensorInfo, descriptorName, 4, "output"); + } + else if (m_Parameters.m_BlockShape.size() == 1) + { + ValidateTensorNumDimensions(inputTensorInfo, descriptorName, 3, "input"); + ValidateTensorNumDimensions(outputTensorInfo, descriptorName, 3, "output"); + } + else + { + throw InvalidArgumentException(descriptorName + ": Invalid Block and Crops size."); + } + + // In a 4D tensor, there will be 2 spatialDimensions (H and W), and the for loop will run twice. + // In a 3D tensor, there will be 1 spatialDimensions, and the for loop will run once. + unsigned int firstSpatialDimension = m_Parameters.m_DataLayout == DataLayout::NCHW ? 2 : 1; + for (unsigned int i = 0; i < m_Parameters.m_BlockShape.size(); ++i) + { + unsigned int spatialDimension = firstSpatialDimension + i; + unsigned int cropSize = m_Parameters.m_Crops[i].first + m_Parameters.m_Crops[i].second; + unsigned int outputSize = inputTensorInfo.GetShape()[spatialDimension] * m_Parameters.m_BlockShape[i]; + if (cropSize > outputSize) + { + throw InvalidArgumentException(descriptorName + ": CropSize must be less than or equal to the uncropped" + "outputSize in dimension: " + to_string(spatialDimension) + "."); + } + } + std::vector supportedTypes = { DataType::BFloat16, diff --git a/src/backends/backendsCommon/test/layerTests/BatchToSpaceNdTestImpl.hpp b/src/backends/backendsCommon/test/layerTests/BatchToSpaceNdTestImpl.hpp index b3007771c9..4f8b7d0193 100644 --- a/src/backends/backendsCommon/test/layerTests/BatchToSpaceNdTestImpl.hpp +++ b/src/backends/backendsCommon/test/layerTests/BatchToSpaceNdTestImpl.hpp @@ -278,6 +278,33 @@ LayerTestResult BatchToSpaceNdNhwcTest7( crops, outputShape, expectedOutput); } +template> +LayerTestResult BatchToSpaceNdNhwcTest8( + armnn::IWorkloadFactory& workloadFactory, + const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, + const armnn::ITensorHandleFactory& tensorHandleFactory) +{ + const unsigned int inputShape[] = {4, 2, 1}; + const unsigned int outputShape[] = {1, 8, 1}; + + std::vector input({ + 1.0f, 2.0f, 3.0f, 4.0f, + 5.0f, 6.0f, 7.0f, 8.0f + }); + + std::vector expectedOutput({ + 1.0f, 3.0f, 5.0f, 7.0f, + 2.0f, 4.0f, 6.0f, 8.0f + }); + + std::vector blockShape {4}; + std::vector> crops = {{0, 0}}; + + return BatchToSpaceNdHelper(workloadFactory, memoryManager, tensorHandleFactory, + armnn::DataLayout::NHWC, inputShape, input, blockShape, + crops, outputShape, expectedOutput); +} + template> LayerTestResult BatchToSpaceNdNchwTest1( armnn::IWorkloadFactory &workloadFactory, diff --git a/src/backends/backendsCommon/test/layerTests/SpaceToBatchNdTestImpl.cpp b/src/backends/backendsCommon/test/layerTests/SpaceToBatchNdTestImpl.cpp index 92876e18bd..4e40692c8c 100644 --- a/src/backends/backendsCommon/test/layerTests/SpaceToBatchNdTestImpl.cpp +++ b/src/backends/backendsCommon/test/layerTests/SpaceToBatchNdTestImpl.cpp @@ -88,6 +88,59 @@ LayerTestResult SpaceToBatchNdTestImpl( outputTensorInfo.GetShape()); } +template +LayerTestResult SpaceToBatchNd3DTestImpl( + armnn::IWorkloadFactory& workloadFactory, + const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, + const armnn::ITensorHandleFactory& tensorHandleFactory, + armnn::TensorInfo& inputTensorInfo, + armnn::TensorInfo& outputTensorInfo, + std::vector& inputData, + std::vector& outputExpectedData, + armnn::SpaceToBatchNdQueueDescriptor descriptor, + const float qScale = 1.0f, + const int32_t qOffset = 0) +{ + IgnoreUnused(memoryManager); + + if(armnn::IsQuantizedType()) + { + inputTensorInfo.SetQuantizationScale(qScale); + inputTensorInfo.SetQuantizationOffset(qOffset); + outputTensorInfo.SetQuantizationScale(qScale); + outputTensorInfo.SetQuantizationOffset(qOffset); + } + + std::vector input = armnnUtils::QuantizedVector(inputData, qScale, qOffset); + std::vector expectedOutput = armnnUtils::QuantizedVector(outputExpectedData, qScale, qOffset); + std::vector actualOutput(outputTensorInfo.GetNumElements()); + + std::unique_ptr inputHandle = tensorHandleFactory.CreateTensorHandle(inputTensorInfo); + std::unique_ptr outputHandle = tensorHandleFactory.CreateTensorHandle(outputTensorInfo); + + armnn::WorkloadInfo info; + AddInputToWorkload(descriptor, info, inputTensorInfo, inputHandle.get()); + AddOutputToWorkload(descriptor, info, outputTensorInfo, outputHandle.get()); + + std::unique_ptr workload = workloadFactory.CreateWorkload(armnn::LayerType::SpaceToBatchNd, + descriptor, + info); + + inputHandle->Allocate(); + outputHandle->Allocate(); + + CopyDataToITensorHandle(inputHandle.get(), input.data()); + + workload->Execute(); + + CopyDataFromITensorHandle(actualOutput.data(), outputHandle.get()); + + return LayerTestResult(actualOutput, + expectedOutput, + outputHandle->GetShape(), + outputTensorInfo.GetShape()); +} + template> LayerTestResult SpaceToBatchNdSimpleTest( armnn::IWorkloadFactory& workloadFactory, @@ -253,6 +306,44 @@ LayerTestResult SpaceToBatchNdPaddingTest( inputTensorInfo, outputTensorInfo, input, outputExpected, desc); } +template> +LayerTestResult SpaceToBatchNdSimple3DTest( + armnn::IWorkloadFactory& workloadFactory, + const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, + const armnn::ITensorHandleFactory& tensorHandleFactory, + armnn::DataLayout dataLayout = armnn::DataLayout::NHWC) +{ + armnn::TensorInfo inputTensorInfo; + armnn::TensorInfo outputTensorInfo; + + unsigned int inputShape[] = {1, 8, 1}; + unsigned int outputShape[] = {4, 2, 1}; + + armnn::SpaceToBatchNdQueueDescriptor desc; + desc.m_Parameters.m_DataLayout = dataLayout; + desc.m_Parameters.m_BlockShape = {4}; + desc.m_Parameters.m_PadList = {{0, 0}}; + + inputTensorInfo = armnn::TensorInfo(3, inputShape, ArmnnType); + outputTensorInfo = armnn::TensorInfo(3, outputShape, ArmnnType); + + std::vector input = std::vector( + { + 1.0f, 3.0f, 5.0f, 7.0f, + 2.0f, 4.0f, 6.0f, 8.0f + }); + + std::vector outputExpected = std::vector( + { + 1.0f, 2.0f, 3.0f, 4.0f, + 5.0f, 6.0f, 7.0f, 8.0f + }); + + return SpaceToBatchNd3DTestImpl( + workloadFactory, memoryManager, tensorHandleFactory, + inputTensorInfo, outputTensorInfo, input, outputExpected, desc); +} + template> LayerTestResult SpaceToBatchNdSimpleNhwcTest( armnn::IWorkloadFactory& workloadFactory, @@ -463,6 +554,16 @@ LayerTestResult SpaceToBatchNdPaddingNhwcFloat32Test( tensorHandleFactory); } +LayerTestResult SpaceToBatchNdSimpleNhwc3DFloat32Test( + armnn::IWorkloadFactory& workloadFactory, + const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, + const armnn::ITensorHandleFactory& tensorHandleFactory) +{ + return SpaceToBatchNdSimple3DTest(workloadFactory, + memoryManager, + tensorHandleFactory); +} + LayerTestResult SpaceToBatchNdSimpleNhwcFloat16Test( armnn::IWorkloadFactory& workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, @@ -503,6 +604,16 @@ LayerTestResult SpaceToBatchNdPaddingNhwcFloat16Test( tensorHandleFactory); } +LayerTestResult SpaceToBatchNdSimpleNhwc3DFloat16Test( + armnn::IWorkloadFactory& workloadFactory, + const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, + const armnn::ITensorHandleFactory& tensorHandleFactory) +{ + return SpaceToBatchNdSimple3DTest(workloadFactory, + memoryManager, + tensorHandleFactory); +} + LayerTestResult SpaceToBatchNdSimpleNhwcUint8Test( armnn::IWorkloadFactory& workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, @@ -543,6 +654,16 @@ LayerTestResult SpaceToBatchNdPaddingNhwcUint8Test( tensorHandleFactory); } +LayerTestResult SpaceToBatchNdSimpleNhwc3DUint8Test( + armnn::IWorkloadFactory& workloadFactory, + const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, + const armnn::ITensorHandleFactory& tensorHandleFactory) +{ + return SpaceToBatchNdSimple3DTest(workloadFactory, + memoryManager, + tensorHandleFactory); +} + LayerTestResult SpaceToBatchNdSimpleUint16Test( armnn::IWorkloadFactory& workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, diff --git a/src/backends/backendsCommon/test/layerTests/SpaceToBatchNdTestImpl.hpp b/src/backends/backendsCommon/test/layerTests/SpaceToBatchNdTestImpl.hpp index 7768b162f2..4e87d6ab6c 100644 --- a/src/backends/backendsCommon/test/layerTests/SpaceToBatchNdTestImpl.hpp +++ b/src/backends/backendsCommon/test/layerTests/SpaceToBatchNdTestImpl.hpp @@ -91,6 +91,11 @@ LayerTestResult SpaceToBatchNdPaddingNhwcFloat32Test( const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, const armnn::ITensorHandleFactory& tensorHandleFactory); +LayerTestResult SpaceToBatchNdSimpleNhwc3DFloat32Test( + armnn::IWorkloadFactory& workloadFactory, + const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, + const armnn::ITensorHandleFactory& tensorHandleFactory); + LayerTestResult SpaceToBatchNdSimpleNhwcFloat16Test( armnn::IWorkloadFactory& workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, @@ -111,6 +116,11 @@ LayerTestResult SpaceToBatchNdPaddingNhwcFloat16Test( const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, const armnn::ITensorHandleFactory& tensorHandleFactory); +LayerTestResult SpaceToBatchNdSimpleNhwc3DFloat16Test( + armnn::IWorkloadFactory& workloadFactory, + const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, + const armnn::ITensorHandleFactory& tensorHandleFactory); + LayerTestResult SpaceToBatchNdSimpleNhwcUint8Test( armnn::IWorkloadFactory& workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, @@ -131,6 +141,11 @@ LayerTestResult SpaceToBatchNdPaddingNhwcUint8Test( const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, const armnn::ITensorHandleFactory& tensorHandleFactory); +LayerTestResult SpaceToBatchNdSimpleNhwc3DUint8Test( + armnn::IWorkloadFactory& workloadFactory, + const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, + const armnn::ITensorHandleFactory& tensorHandleFactory); + LayerTestResult SpaceToBatchNdSimpleUint16Test( armnn::IWorkloadFactory& workloadFactory, const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, -- cgit v1.2.1