From b4ef16334900af33bf4321f28c90f62bf32238cd Mon Sep 17 00:00:00 2001 From: Colm Donelan Date: Thu, 1 Feb 2024 15:00:43 +0000 Subject: IVGCVSW-7854 Remove/rewrite asserts in the backends. * Identify usages of ARMNN_ASSERT that should be proper exceptions. * Change ARMNN_ASSERT in Doctests to CHECK. * Verify any remaining assertions are reasonable. Signed-off-by: Colm Donelan Change-Id: Ifd1f2a5a4bb60135e8654305035ec70e09c4dc2d --- src/backends/aclCommon/ArmComputeSubgraphUtils.hpp | 8 +------- src/backends/aclCommon/ArmComputeTensorUtils.cpp | 7 +++---- src/backends/aclCommon/ArmComputeUtils.hpp | 13 ++++++------- src/backends/aclCommon/BaseMemoryManager.cpp | 10 ++-------- 4 files changed, 12 insertions(+), 26 deletions(-) (limited to 'src/backends/aclCommon') diff --git a/src/backends/aclCommon/ArmComputeSubgraphUtils.hpp b/src/backends/aclCommon/ArmComputeSubgraphUtils.hpp index a44acb0f54..9b889141be 100644 --- a/src/backends/aclCommon/ArmComputeSubgraphUtils.hpp +++ b/src/backends/aclCommon/ArmComputeSubgraphUtils.hpp @@ -1,12 +1,11 @@ // -// Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2020-2024 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include -#include #include #include @@ -330,11 +329,6 @@ std::vector ChainReduceLayers(OptimizationViews& optimizatio layers.emplace_back(replacementLayer); } - - // Check if the TensorInfo from the last layer equals the inferred output from the original layer. - ARMNN_ASSERT(baseLayer->GetOutputSlot(0).GetTensorInfo() == - PolymorphicDowncast(layers.back())->GetOutputSlot().GetTensorInfo()); - return layers; } diff --git a/src/backends/aclCommon/ArmComputeTensorUtils.cpp b/src/backends/aclCommon/ArmComputeTensorUtils.cpp index a11b966f34..c5b4fa157e 100644 --- a/src/backends/aclCommon/ArmComputeTensorUtils.cpp +++ b/src/backends/aclCommon/ArmComputeTensorUtils.cpp @@ -2,10 +2,11 @@ // Copyright © 2017-2024 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // + +#include #include #include -#include "armnn/Exceptions.hpp" #include "ArmComputeUtils.hpp" #include @@ -43,7 +44,6 @@ arm_compute::DataType GetArmComputeDataType(armnn::DataType dataType, bool multi case armnn::DataType::Signed32: return arm_compute::DataType::S32; default: - ARMNN_ASSERT_MSG(false, "Unknown data type"); return arm_compute::DataType::UNKNOWN; } } @@ -75,8 +75,7 @@ armnn::DataType GetArmNNDataType(arm_compute::DataType dataType) case arm_compute::DataType::S32: return armnn::DataType::Signed32; default: - ARMNN_ASSERT_MSG(false, "Unknown data type"); - return armnn::DataType::Float32; + throw InvalidArgumentException("Unknown arm_compute::DataType data type"); } } diff --git a/src/backends/aclCommon/ArmComputeUtils.hpp b/src/backends/aclCommon/ArmComputeUtils.hpp index 9a30a7456e..d7025aa5e2 100644 --- a/src/backends/aclCommon/ArmComputeUtils.hpp +++ b/src/backends/aclCommon/ArmComputeUtils.hpp @@ -1,12 +1,12 @@ // -// Copyright © 2017-2023 Arm Ltd. All rights reserved. +// Copyright © 2017-2024 Arm Ltd. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include +#include #include -#include #include #include #include @@ -233,8 +233,7 @@ inline T ComputeSoftmaxAclAxis(const SoftmaxDescriptor& softmaxDesc, const armnn } unsigned int dim = tensor.GetNumDimensions(); - - ARMNN_ASSERT(dim != 0); + ARMNN_THROW_INVALIDARG_MSG_IF_FALSE(dim != 0, "The number of dimensions in this tensor cannot be zero."); // Currently ArmNN support axis 1. auto aclAxis = (static_cast(dim) - 1); @@ -274,9 +273,9 @@ inline int ComputeAclAxis(const int& armnnAxis, const armnn::TensorInfo& tensor) { int rank = static_cast(tensor.GetNumDimensions()); - ARMNN_ASSERT(rank != 0); - ARMNN_ASSERT((-1 * rank) <= armnnAxis); - ARMNN_ASSERT(armnnAxis < rank); + ARMNN_THROW_INVALIDARG_MSG_IF_FALSE(rank != 0, "The number of dimensions in this tensor cannot be zero."); + ARMNN_THROW_INVALIDARG_MSG_IF_FALSE(armnnAxis < rank, "Incompatible value of armnnAxis."); + ARMNN_THROW_INVALIDARG_MSG_IF_FALSE((-1 * rank) <= armnnAxis, "Incompatible value of armnnAxis."); int sign = (armnnAxis < 0) ? -1 : 1; int aclAxis = sign * rank - 1 - armnnAxis; diff --git a/src/backends/aclCommon/BaseMemoryManager.cpp b/src/backends/aclCommon/BaseMemoryManager.cpp index 206cf9b230..50517cb54c 100644 --- a/src/backends/aclCommon/BaseMemoryManager.cpp +++ b/src/backends/aclCommon/BaseMemoryManager.cpp @@ -1,5 +1,5 @@ // -// Copyright © 2017-2023 Arm Ltd. All rights reserved. +// Copyright © 2017-2024 Arm Ltd. All rights reserved. // SPDX-License-Identifier: MIT // #include "BaseMemoryManager.hpp" @@ -18,7 +18,7 @@ namespace armnn BaseMemoryManager::BaseMemoryManager(std::shared_ptr alloc, MemoryAffinity memoryAffinity) { - ARMNN_ASSERT(alloc); + ARMNN_THROW_INVALIDARG_MSG_IF_FALSE(alloc, "A null allocator has been passed to BaseMemoryManager."); m_Allocator = std::move(alloc); m_IntraLayerMemoryMgr = CreateArmComputeMemoryManager(memoryAffinity); @@ -50,30 +50,24 @@ void BaseMemoryManager::Acquire() static const size_t s_NumPools = 1; // Allocate memory pools for intra-layer memory manager - ARMNN_ASSERT(m_IntraLayerMemoryMgr); m_IntraLayerMemoryMgr->populate(*m_Allocator, s_NumPools); // Allocate memory pools for inter-layer memory manager - ARMNN_ASSERT(m_InterLayerMemoryMgr); m_InterLayerMemoryMgr->populate(*m_Allocator, s_NumPools); // Acquire inter-layer memory group. NOTE: This has to come after allocating the pools - ARMNN_ASSERT(m_InterLayerMemoryGroup); m_InterLayerMemoryGroup->acquire(); } void BaseMemoryManager::Release() { // Release inter-layer memory group. NOTE: This has to come before releasing the pools - ARMNN_ASSERT(m_InterLayerMemoryGroup); m_InterLayerMemoryGroup->release(); // Release memory pools managed by intra-layer memory manager - ARMNN_ASSERT(m_IntraLayerMemoryMgr); m_IntraLayerMemoryMgr->clear(); // Release memory pools managed by inter-layer memory manager - ARMNN_ASSERT(m_InterLayerMemoryMgr); m_InterLayerMemoryMgr->clear(); } #else -- cgit v1.2.1