From 10b4dfd8e9ccd7a03df7bb053ee1c644cb37f8ab Mon Sep 17 00:00:00 2001
From: David Beck <david.beck@arm.com>
Date: Wed, 19 Sep 2018 12:03:20 +0100
Subject: IVGCVSW-1897 : build infrastructure for the src/backends folder

Change-Id: I7ebafb675ccc77ad54d1deb01412a8379a5356bb
---
 .../ClDepthwiseConvolutionUint8Workload.cpp        | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 src/backends/ClWorkloads/ClDepthwiseConvolutionUint8Workload.cpp

(limited to 'src/backends/ClWorkloads/ClDepthwiseConvolutionUint8Workload.cpp')

diff --git a/src/backends/ClWorkloads/ClDepthwiseConvolutionUint8Workload.cpp b/src/backends/ClWorkloads/ClDepthwiseConvolutionUint8Workload.cpp
new file mode 100644
index 0000000000..af5836e908
--- /dev/null
+++ b/src/backends/ClWorkloads/ClDepthwiseConvolutionUint8Workload.cpp
@@ -0,0 +1,40 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "ClDepthwiseConvolutionUint8Workload.hpp"
+
+#include "backends/CpuTensorHandle.hpp"
+
+#include "ClWorkloadUtils.hpp"
+
+namespace armnn
+{
+
+ClDepthwiseConvolutionUint8Workload::ClDepthwiseConvolutionUint8Workload(
+    const DepthwiseConvolution2dQueueDescriptor& descriptor,
+    const WorkloadInfo& info)
+    : ClDepthwiseConvolutionBaseWorkload(descriptor, info)
+{
+    InitialiseArmComputeClTensorData(*m_KernelTensor, m_Data.m_Weight->template GetConstTensor<uint8_t>());
+
+    if (m_BiasTensor)
+    {
+        InitialiseArmComputeClTensorData(*m_BiasTensor, m_Data.m_Bias->template GetConstTensor<int32_t>());
+    }
+
+    m_DepthwiseConvolutionLayer->prepare();
+    FreeUnusedTensors();
+}
+
+void ClDepthwiseConvolutionUint8Workload::Execute() const
+{
+    ARMNN_SCOPED_PROFILING_EVENT_CL("ClDepthwiseConvolutionUint8Workload_Execute");
+    BOOST_ASSERT(m_DepthwiseConvolutionLayer);
+
+    m_DepthwiseConvolutionLayer->run();
+}
+
+} //namespace armnn
+
-- 
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