From e7a86a4a3363993fb41b1ea62f23b3643b8b0c78 Mon Sep 17 00:00:00 2001
From: Francis Murtagh <francis.murtagh@arm.com>
Date: Wed, 29 Aug 2018 12:42:10 +0100
Subject: IVGCVSW-1200 Division layer

	*IVGCVSW-1772 Create QueueDescriptors
	*IVGCVSW-1773 Add a CL implementation of the DivisionWorkload
	*IVGCVSW-1774 Add Neon implementation of the DivisionWorkload
	*IVGCVSW-1775 Add a Ref implementation of the DivisionWorkload
	*IVGCVSW-1776 Add a Division Layer
	* Added simple division unit tests with broadcasting

Change-Id: I05751fb7f868789f6c06f91e8d25e52b4f12ab5e
---
 src/armnn/backends/WorkloadData.cpp | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'src/armnn/backends/WorkloadData.cpp')

diff --git a/src/armnn/backends/WorkloadData.cpp b/src/armnn/backends/WorkloadData.cpp
index aa763801ce..626b1ebd7e 100644
--- a/src/armnn/backends/WorkloadData.cpp
+++ b/src/armnn/backends/WorkloadData.cpp
@@ -798,4 +798,17 @@ void ConvertFp16ToFp32QueueDescriptor::Validate(const WorkloadInfo& workloadInfo
                               "output");
 }
 
+void DivisionQueueDescriptor::Validate(const WorkloadInfo& workloadInfo) const
+{
+    ValidateTwoInputs(workloadInfo, "DivisionQueueDescriptor");
+    ValidateSingleOutput(workloadInfo, "DivisionQueueDescriptor");
+
+    ValidateBroadcastTensorShapesMatch(workloadInfo.m_InputTensorInfos[0],
+                                       workloadInfo.m_InputTensorInfos[1],
+                                       workloadInfo.m_OutputTensorInfos[0],
+                                       "DivisionQueueDescriptor",
+                                       "first input",
+                                       "second input");
+}
+
 } //namespace armnn
-- 
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