From e7a86a4a3363993fb41b1ea62f23b3643b8b0c78 Mon Sep 17 00:00:00 2001 From: Francis Murtagh Date: Wed, 29 Aug 2018 12:42:10 +0100 Subject: IVGCVSW-1200 Division layer *IVGCVSW-1772 Create QueueDescriptors *IVGCVSW-1773 Add a CL implementation of the DivisionWorkload *IVGCVSW-1774 Add Neon implementation of the DivisionWorkload *IVGCVSW-1775 Add a Ref implementation of the DivisionWorkload *IVGCVSW-1776 Add a Division Layer * Added simple division unit tests with broadcasting Change-Id: I05751fb7f868789f6c06f91e8d25e52b4f12ab5e --- .../ClWorkloads/ClDivisionFloatWorkload.cpp | 49 ++++++++++++++++++++++ .../ClWorkloads/ClDivisionFloatWorkload.hpp | 30 +++++++++++++ 2 files changed, 79 insertions(+) create mode 100644 src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.cpp create mode 100644 src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.hpp (limited to 'src/armnn/backends/ClWorkloads') diff --git a/src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.cpp b/src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.cpp new file mode 100644 index 0000000000..07345c345c --- /dev/null +++ b/src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.cpp @@ -0,0 +1,49 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "ClDivisionFloatWorkload.hpp" +#include "backends/ClTensorHandle.hpp" +#include "backends/CpuTensorHandle.hpp" + +namespace armnn +{ + +arm_compute::Status ClDivisionWorkloadValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output) +{ + const arm_compute::TensorInfo aclInput1 = armcomputetensorutils::BuildArmComputeTensorInfo(input0); + const arm_compute::TensorInfo aclInput2 = armcomputetensorutils::BuildArmComputeTensorInfo(input1); + const arm_compute::TensorInfo aclOutput = armcomputetensorutils::BuildArmComputeTensorInfo(output); + + // At the time of writing, configure() will fail if a rounding policy other than TO_ZERO is supplied to it, + // when providing a scale of 1.0 for F32 tensors, even though the provided rounding policy appears to be + // ignored for F32 tensors. + return arm_compute::CLArithmeticDivision::validate(&aclInput1, &aclInput2, &aclOutput); +} + + +ClDivisionFloatWorkload::ClDivisionFloatWorkload(const DivisionQueueDescriptor& descriptor, + const WorkloadInfo& info) + : FloatWorkload(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClDivisionFloatWorkload", 2, 1); + + arm_compute::ICLTensor& input0 = static_cast(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& input1 = static_cast(m_Data.m_Inputs[1])->GetTensor(); + arm_compute::ICLTensor& output = static_cast(m_Data.m_Outputs[0])->GetTensor(); + // Construct + m_ArithmeticDivision.configure(&input0, &input1, &output); +} + +void ClDivisionFloatWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClDivisionFloatWorkload_Execute"); + + // Executes the layer. + m_ArithmeticDivision.run(); +} + +} //namespace armnn diff --git a/src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.hpp b/src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.hpp new file mode 100644 index 0000000000..bd06d38e8b --- /dev/null +++ b/src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.hpp @@ -0,0 +1,30 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#pragma once + +#include "backends/ClWorkloadUtils.hpp" + +namespace armnn +{ + +arm_compute::Status ClDivisionWorkloadValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output); + +class ClDivisionFloatWorkload : public FloatWorkload +{ +public: + ClDivisionFloatWorkload(const DivisionQueueDescriptor& descriptor, const + WorkloadInfo& info); + + using FloatWorkload::FloatWorkload; + void Execute() const override; + +private: + mutable arm_compute::CLArithmeticDivision m_ArithmeticDivision; +}; + +} //namespace armnn -- cgit v1.2.1