From 9e53a35b66b1ec7ceee7c712380a13596175b83b Mon Sep 17 00:00:00 2001 From: arovir01 Date: Fri, 31 Aug 2018 15:26:35 +0100 Subject: IVGCVSW-1784: Rename float32 workloads for ACL Change-Id: I98bdfe9cb12c663d1d5cfa456e2cc967d70ab22b --- .../ClWorkloads/ClReshapeFloatWorkload.cpp | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 src/armnn/backends/ClWorkloads/ClReshapeFloatWorkload.cpp (limited to 'src/armnn/backends/ClWorkloads/ClReshapeFloatWorkload.cpp') diff --git a/src/armnn/backends/ClWorkloads/ClReshapeFloatWorkload.cpp b/src/armnn/backends/ClWorkloads/ClReshapeFloatWorkload.cpp new file mode 100644 index 0000000000..645544b75d --- /dev/null +++ b/src/armnn/backends/ClWorkloads/ClReshapeFloatWorkload.cpp @@ -0,0 +1,31 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "ClReshapeFloatWorkload.hpp" +#include "backends/ClTensorHandle.hpp" +#include "backends/CpuTensorHandle.hpp" + +namespace armnn +{ + +ClReshapeFloatWorkload::ClReshapeFloatWorkload(const ReshapeQueueDescriptor& descriptor, const WorkloadInfo& info) + : FloatWorkload(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClReshapeFloatWorkload", 1, 1); + + arm_compute::ICLTensor& input = static_cast(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& output = static_cast(m_Data.m_Outputs[0])->GetTensor(); + + m_Layer.configure(&input, &output); +} + +void ClReshapeFloatWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClReshapeFloatWorkload_Execute"); + m_Layer.run(); +} + +} //namespace armnn + -- cgit v1.2.1