From 9e53a35b66b1ec7ceee7c712380a13596175b83b Mon Sep 17 00:00:00 2001 From: arovir01 Date: Fri, 31 Aug 2018 15:26:35 +0100 Subject: IVGCVSW-1784: Rename float32 workloads for ACL Change-Id: I98bdfe9cb12c663d1d5cfa456e2cc967d70ab22b --- .../ClWorkloads/ClAdditionFloatWorkload.cpp | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.cpp (limited to 'src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.cpp') diff --git a/src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.cpp b/src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.cpp new file mode 100644 index 0000000000..089b84a33f --- /dev/null +++ b/src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.cpp @@ -0,0 +1,22 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "ClAdditionFloatWorkload.hpp" + +#include "backends/ClTensorHandle.hpp" +#include "backends/CpuTensorHandle.hpp" +#include "backends/ArmComputeTensorUtils.hpp" + +namespace armnn +{ +using namespace armcomputetensorutils; + +void ClAdditionFloatWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClAdditionFloatWorkload_Execute"); + ClAdditionBaseWorkload::Execute(); +} + +} //namespace armnn -- cgit v1.2.1