From 03c7ff3f6188240baaeaeb405a357a0c58195fec Mon Sep 17 00:00:00 2001 From: Nikhil Raj Date: Tue, 22 Aug 2023 12:00:04 +0100 Subject: IVGCVSW-7702 Update Doxygen Docu for 23.08 Signed-off-by: Nikhil Raj Change-Id: I357a9f7e47614589327c1ac5d95b6224ff77103d --- latest/_mem_sync_workload_8cpp_source.html | 170 +++++++++++++++++++++++++++++ 1 file changed, 170 insertions(+) create mode 100644 latest/_mem_sync_workload_8cpp_source.html (limited to 'latest/_mem_sync_workload_8cpp_source.html') diff --git a/latest/_mem_sync_workload_8cpp_source.html b/latest/_mem_sync_workload_8cpp_source.html new file mode 100644 index 0000000000..9ff99a1eba --- /dev/null +++ b/latest/_mem_sync_workload_8cpp_source.html @@ -0,0 +1,170 @@ + + + + + + + + +Arm NN: src/backends/backendsCommon/MemSyncWorkload.cpp Source File + + + + + + + + + + + + + + + + +
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+  23.08 +
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MemSyncWorkload.cpp
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+Go to the documentation of this file.
1 //
+
2 // Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
+
3 // SPDX-License-Identifier: MIT
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4 //
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5 
+
6 #include <ResolveType.hpp>
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7 
+
8 #include <backendsCommon/MemSyncWorkload.hpp>
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9 #include <armnn/backends/TensorHandle.hpp>
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10 
+
11 #include <cstring>
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12 
+
13 namespace armnn
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14 {
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15 
+
16 SyncMemGenericWorkload::SyncMemGenericWorkload(const MemSyncQueueDescriptor& descriptor,
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17  const WorkloadInfo& info)
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18  : BaseWorkload<MemSyncQueueDescriptor>(descriptor, info)
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19 {
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20  m_TensorHandle = descriptor.m_Inputs[0];
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21 }
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22 
+
23 void SyncMemGenericWorkload::Execute() const
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24 {
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25  ARMNN_SCOPED_PROFILING_EVENT(Compute::Undefined, "SyncMemGeneric_Execute");
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26  m_TensorHandle->Map(true);
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27  m_TensorHandle->Unmap();
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28 }
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29 
+
30 void SyncMemGenericWorkload::ExecuteAsync(ExecutionData& executionData)
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31 {
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32  ARMNN_SCOPED_PROFILING_EVENT(Compute::Undefined, "SyncMemGeneric_Execute_WorkingMemDescriptor");
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33 
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34  WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
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35  workingMemDescriptor->m_Inputs[0]->Map(true);
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36  workingMemDescriptor->m_Inputs[0]->Unmap();
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37 }
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38 
+
39 } //namespace armnn
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+ + +
armnn::SyncMemGenericWorkload::ExecuteAsync
void ExecuteAsync(ExecutionData &executionData) override
Definition: MemSyncWorkload.cpp:30
+ + +
ARMNN_SCOPED_PROFILING_EVENT
#define ARMNN_SCOPED_PROFILING_EVENT(backendId, name)
Definition: Profiling.hpp:220
+
armnn::WorkloadInfo
Contains information about TensorInfos of a layer.
Definition: WorkloadInfo.hpp:16
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armnn::ITensorHandle::Unmap
virtual void Unmap() const =0
Unmap the tensor data.
+ + +
armnn::SyncMemGenericWorkload::SyncMemGenericWorkload
SyncMemGenericWorkload(const MemSyncQueueDescriptor &descriptor, const WorkloadInfo &info)
Definition: MemSyncWorkload.cpp:16
+
armnn::SyncMemGenericWorkload::Execute
void Execute() const override
Definition: MemSyncWorkload.cpp:23
+ + +
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_quick_start.dox:6
+ + +
armnn::QueueDescriptor::m_Inputs
std::vector< ITensorHandle * > m_Inputs
Definition: WorkloadData.hpp:26
+
armnn::ITensorHandle::Map
virtual const void * Map(bool blocking=true) const =0
Map the tensor data for access.
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