From dc032fca290deb39af65050c254a701596b53fa8 Mon Sep 17 00:00:00 2001 From: Sadik Armagan Date: Tue, 19 Jan 2021 17:24:21 +0000 Subject: IVGCVSW-5399 'TfLiteDelegate: Implement the ArgMinMax operators' * Added ARG_MIN and ARG_MAX support to armnn_delegate Signed-off-by: Sadik Armagan Change-Id: Ia000c4b64378e28320164edd4df2902ca13dcda6 --- delegate/CMakeLists.txt | 2 + delegate/TensorFlowLiteDelegateSupport.md | 4 + delegate/src/ArgMinMax.hpp | 120 ++++++++++++++++-- delegate/src/test/ArgMinMaxTest.cpp | 174 ++++++++++++++++++++++++++ delegate/src/test/ArgMinMaxTestHelper.hpp | 198 ++++++++++++++++++++++++++++++ 5 files changed, 490 insertions(+), 8 deletions(-) create mode 100644 delegate/src/test/ArgMinMaxTest.cpp create mode 100644 delegate/src/test/ArgMinMaxTestHelper.hpp diff --git a/delegate/CMakeLists.txt b/delegate/CMakeLists.txt index 9f64353d9a..8383722628 100644 --- a/delegate/CMakeLists.txt +++ b/delegate/CMakeLists.txt @@ -108,6 +108,8 @@ if(BUILD_UNIT_TESTS) list(APPEND armnnDelegate_unittest_sources src/test/ActivationTest.cpp src/test/ActivationTestHelper.hpp + src/test/ArgMinMaxTest.cpp + src/test/ArgMinMaxTestHelper.hpp src/test/ArmnnDelegateTest.cpp src/test/ComparisonTest.cpp src/test/ComparisonTestHelper.hpp diff --git a/delegate/TensorFlowLiteDelegateSupport.md b/delegate/TensorFlowLiteDelegateSupport.md index e506b85f23..dd4cbace7b 100644 --- a/delegate/TensorFlowLiteDelegateSupport.md +++ b/delegate/TensorFlowLiteDelegateSupport.md @@ -10,6 +10,10 @@ The Arm NN SDK TensorFlow Lite delegate currently supports the following operato * ADD +* ARGMAX + +* ARGMIN + * AVERAGE_POOL_2D, Supported Fused Activation: RELU , RELU6 , TANH, NONE * CONCATENATION, Supported Fused Activation: RELU , RELU6 , TANH, NONE diff --git a/delegate/src/ArgMinMax.hpp b/delegate/src/ArgMinMax.hpp index 367ef2ed14..090d18ef65 100644 --- a/delegate/src/ArgMinMax.hpp +++ b/delegate/src/ArgMinMax.hpp @@ -5,11 +5,10 @@ #pragma once -#include - #include #include #include +#include #include namespace armnnDelegate @@ -21,13 +20,118 @@ TfLiteStatus VisitArgMinMaxOperator(DelegateData& delegateData, int nodeIndex, int32_t argMinMaxOperatorCode) { - armnn::IgnoreUnused(delegateData, - tfLiteContext, - tfLiteNode, - nodeIndex, - argMinMaxOperatorCode); + TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); + TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); + + const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; + const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; + if (!IsValid(tfLiteContext, tfLiteInputTensor, argMinMaxOperatorCode, nodeIndex)) + { + return kTfLiteError; + } + + const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; + if (!IsValid(tfLiteContext, tfLiteOutputTensor, argMinMaxOperatorCode, nodeIndex)) + { + return kTfLiteError; + } + + const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + + // Get const axis value from model and set it to descriptor. + const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; + if (!IsValid(tfLiteContext, tfLiteAxisTensor, argMinMaxOperatorCode, nodeIndex)) + { + return kTfLiteError; + } + + armnn::ArgMinMaxDescriptor desc; + // Get the axis value from the input tensor + switch (tfLiteAxisTensor.type) + { + case kTfLiteInt32: + case kTfLiteInt64: + desc.m_Axis = tflite::GetTensorData(&tfLiteAxisTensor)[0]; + break; + default: + TF_LITE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnDelegate: Axis value data type is not supported in operator #%d node #%d: ", + argMinMaxOperatorCode, nodeIndex); + return kTfLiteError; + } + + // If output_type is int32 then set Signed32 else Signed64. Default type is Signed64. + if (argMinMaxOperatorCode == kTfLiteBuiltinArgMax) + { + desc.m_Function = armnn::ArgMinMaxFunction::Max; + auto* argMaxParameters = reinterpret_cast(tfLiteNode->builtin_data); + switch (argMaxParameters->output_type) + { + case kTfLiteInt32: + desc.m_Output_Type = armnn::DataType::Signed32; + break; + case kTfLiteInt64: + desc.m_Output_Type = armnn::DataType::Signed64; + break; + default: + TF_LITE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnDelegate: output_type data type is not supported in operator #%d node #%d: ", + argMinMaxOperatorCode, nodeIndex); + return kTfLiteError; + } + } + else + { + desc.m_Function = armnn::ArgMinMaxFunction::Min; + auto* argMinParameters = reinterpret_cast(tfLiteNode->builtin_data); + switch (argMinParameters->output_type) + { + case kTfLiteInt32: + desc.m_Output_Type = armnn::DataType::Signed32; + break; + case kTfLiteInt64: + desc.m_Output_Type = armnn::DataType::Signed64; + break; + default: + TF_LITE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnDelegate: output_type data type is not supported in operator #%d node #%d: ", + argMinMaxOperatorCode, nodeIndex); + return kTfLiteError; + } + } + + bool isSupported = false; + auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) + { + FORWARD_LAYER_SUPPORT_FUNC(__func__, + tfLiteContext, + IsArgMinMaxSupported, + delegateData.m_Backends, + isSupported, + inputTensorInfo, + outInfo, + desc); + }; + + if (!delegateData.m_Network) + { + validateFunc(outputTensorInfo, isSupported); + return isSupported ? kTfLiteOk : kTfLiteError; + } + + // Add an ArgMinMax layer + armnn::IConnectableLayer* layer = delegateData.m_Network->AddArgMinMaxLayer(desc); + ARMNN_ASSERT(layer != nullptr); + + armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); + outputSlot.SetTensorInfo(outputTensorInfo); - return kTfLiteError; + // Connect + return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate diff --git a/delegate/src/test/ArgMinMaxTest.cpp b/delegate/src/test/ArgMinMaxTest.cpp new file mode 100644 index 0000000000..bf60a77cb2 --- /dev/null +++ b/delegate/src/test/ArgMinMaxTest.cpp @@ -0,0 +1,174 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ArgMinMaxTestHelper.hpp" + +#include + +#include +#include + +#include + +namespace armnnDelegate +{ + +void ArgMaxFP32Test(std::vector& backends, int axisValue) +{ + // Set input data + std::vector inputShape { 1, 3, 2, 4 }; + std::vector outputShape { 1, 3, 4 }; + std::vector axisShape { 1 }; + + std::vector inputValues = { 1.0f, 2.0f, 3.0f, 4.0f, + 5.0f, 6.0f, 7.0f, 8.0f, + + 10.0f, 20.0f, 30.0f, 40.0f, + 50.0f, 60.0f, 70.0f, 80.0f, + + 100.0f, 200.0f, 300.0f, 400.0f, + 500.0f, 600.0f, 700.0f, 800.0f }; + + std::vector expectedOutputValues = { 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1 }; + + ArgMinMaxTest(tflite::BuiltinOperator_ARG_MAX, + ::tflite::TensorType_FLOAT32, + backends, + inputShape, + axisShape, + outputShape, + inputValues, + expectedOutputValues, + axisValue, + ::tflite::TensorType_INT32); +} + +void ArgMinFP32Test(std::vector& backends, int axisValue) +{ + // Set input data + std::vector inputShape { 1, 3, 2, 4 }; + std::vector outputShape { 1, 3, 2 }; + std::vector axisShape { 1 }; + + std::vector inputValues = { 1.0f, 2.0f, 3.0f, 4.0f, + 5.0f, 6.0f, 7.0f, 8.0f, + + 10.0f, 20.0f, 30.0f, 40.0f, + 50.0f, 60.0f, 70.0f, 80.0f, + + 100.0f, 200.0f, 300.0f, 400.0f, + 500.0f, 600.0f, 700.0f, 800.0f }; + + std::vector expectedOutputValues = { 0, 0, + 0, 0, + 0, 0 }; + + ArgMinMaxTest(tflite::BuiltinOperator_ARG_MIN, + ::tflite::TensorType_FLOAT32, + backends, + inputShape, + axisShape, + outputShape, + inputValues, + expectedOutputValues, + axisValue, + ::tflite::TensorType_INT32); +} + +void ArgMaxUint8Test(std::vector& backends, int axisValue) +{ + // Set input data + std::vector inputShape { 1, 1, 1, 5 }; + std::vector outputShape { 1, 1, 1 }; + std::vector axisShape { 1 }; + + std::vector inputValues = { 5, 2, 8, 10, 9 }; + + std::vector expectedOutputValues = { 3 }; + + ArgMinMaxTest(tflite::BuiltinOperator_ARG_MAX, + ::tflite::TensorType_UINT8, + backends, + inputShape, + axisShape, + outputShape, + inputValues, + expectedOutputValues, + axisValue, + ::tflite::TensorType_INT32); +} + +TEST_SUITE("ArgMinMax_CpuRefTests") +{ + +TEST_CASE ("ArgMaxFP32Test_CpuRef_Test") +{ + std::vector backends = { armnn::Compute::CpuRef }; + ArgMaxFP32Test(backends, 2); +} + +TEST_CASE ("ArgMinFP32Test_CpuRef_Test") +{ + std::vector backends = { armnn::Compute::CpuRef }; + ArgMinFP32Test(backends, 3); +} + +TEST_CASE ("ArgMaxUint8Test_CpuRef_Test") +{ + std::vector backends = { armnn::Compute::CpuRef }; + ArgMaxUint8Test(backends, -1); +} + +} // TEST_SUITE("ArgMinMax_CpuRefTests") + +TEST_SUITE("ArgMinMax_CpuAccTests") +{ + +TEST_CASE ("ArgMaxFP32Test_CpuAcc_Test") +{ + std::vector backends = { armnn::Compute::CpuAcc }; + ArgMaxFP32Test(backends, 2); +} + +TEST_CASE ("ArgMinFP32Test_CpuAcc_Test") +{ + std::vector backends = { armnn::Compute::CpuAcc }; + ArgMinFP32Test(backends, 3); +} + +TEST_CASE ("ArgMaxUint8Test_CpuAcc_Test") +{ + std::vector backends = { armnn::Compute::CpuAcc }; + ArgMaxUint8Test(backends, -1); +} + +} // TEST_SUITE("ArgMinMax_CpuAccTests") + +TEST_SUITE("ArgMinMax_GpuAccTests") +{ + +TEST_CASE ("ArgMaxFP32Test_GpuAcc_Test") +{ + std::vector backends = { armnn::Compute::GpuAcc }; + ArgMaxFP32Test(backends, 2); +} + +TEST_CASE ("ArgMinFP32Test_GpuAcc_Test") +{ + std::vector backends = { armnn::Compute::GpuAcc }; + ArgMinFP32Test(backends, 3); +} + +TEST_CASE ("ArgMaxUint8Test_GpuAcc_Test") +{ + std::vector backends = { armnn::Compute::GpuAcc }; + ArgMaxUint8Test(backends, -1); +} + +} // TEST_SUITE("ArgMinMax_GpuAccTests") + +} // namespace armnnDelegate \ No newline at end of file diff --git a/delegate/src/test/ArgMinMaxTestHelper.hpp b/delegate/src/test/ArgMinMaxTestHelper.hpp new file mode 100644 index 0000000000..d071653ac7 --- /dev/null +++ b/delegate/src/test/ArgMinMaxTestHelper.hpp @@ -0,0 +1,198 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include "TestUtils.hpp" + +#include + +#include +#include +#include +#include +#include +#include + +#include + +namespace +{ + +template +std::vector CreateArgMinMaxTfLiteModel(tflite::BuiltinOperator argMinMaxOperatorCode, + tflite::TensorType tensorType, + const std::vector& inputTensorShape, + const std::vector& axisTensorShape, + const std::vector& outputTensorShape, + const std::vector axisValue, + tflite::TensorType outputType, + float quantScale = 1.0f, + int quantOffset = 0) +{ + using namespace tflite; + flatbuffers::FlatBufferBuilder flatBufferBuilder; + + auto quantizationParameters = + CreateQuantizationParameters(flatBufferBuilder, + 0, + 0, + flatBufferBuilder.CreateVector({ quantScale }), + flatBufferBuilder.CreateVector({ quantOffset })); + + auto inputTensor = CreateTensor(flatBufferBuilder, + flatBufferBuilder.CreateVector(inputTensorShape.data(), + inputTensorShape.size()), + tensorType, + 0, + flatBufferBuilder.CreateString("input"), + quantizationParameters); + + auto axisTensor = CreateTensor(flatBufferBuilder, + flatBufferBuilder.CreateVector(axisTensorShape.data(), + axisTensorShape.size()), + tflite::TensorType_INT32, + 1, + flatBufferBuilder.CreateString("axis")); + + auto outputTensor = CreateTensor(flatBufferBuilder, + flatBufferBuilder.CreateVector(outputTensorShape.data(), + outputTensorShape.size()), + outputType, + 2, + flatBufferBuilder.CreateString("output"), + quantizationParameters); + + std::vector> tensors = { inputTensor, axisTensor, outputTensor }; + + std::vector> buffers; + buffers.push_back(CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector({}))); + buffers.push_back( + CreateBuffer(flatBufferBuilder, + flatBufferBuilder.CreateVector(reinterpret_cast(axisValue.data()), + sizeof(OutputT)))); + buffers.push_back(CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector({}))); + + std::vector operatorInputs = {{ 0, 1 }}; + std::vector subgraphInputs = {{ 0, 1 }}; + + tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_ArgMaxOptions; + flatbuffers::Offset operatorBuiltinOptions = CreateArgMaxOptions(flatBufferBuilder, outputType).Union(); + + if (argMinMaxOperatorCode == tflite::BuiltinOperator_ARG_MIN) + { + operatorBuiltinOptionsType = BuiltinOptions_ArgMinOptions; + operatorBuiltinOptions = CreateArgMinOptions(flatBufferBuilder, outputType).Union(); + } + + // create operator + const std::vector operatorOutputs{{ 2 }}; + flatbuffers::Offset argMinMaxOperator = + CreateOperator(flatBufferBuilder, + 0, + flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), + flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), + operatorBuiltinOptionsType, + operatorBuiltinOptions); + + const std::vector subgraphOutputs{{ 2 }}; + flatbuffers::Offset subgraph = + CreateSubGraph(flatBufferBuilder, + flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), + flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), + flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), + flatBufferBuilder.CreateVector(&argMinMaxOperator, 1)); + + flatbuffers::Offset modelDescription = + flatBufferBuilder.CreateString("ArmnnDelegate: ArgMinMax Operator Model"); + flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, + argMinMaxOperatorCode); + + flatbuffers::Offset flatbufferModel = + CreateModel(flatBufferBuilder, + TFLITE_SCHEMA_VERSION, + flatBufferBuilder.CreateVector(&operatorCode, 1), + flatBufferBuilder.CreateVector(&subgraph, 1), + modelDescription, + flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); + + flatBufferBuilder.Finish(flatbufferModel); + + return std::vector(flatBufferBuilder.GetBufferPointer(), + flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); +} + +template +void ArgMinMaxTest(tflite::BuiltinOperator argMinMaxOperatorCode, + tflite::TensorType tensorType, + const std::vector& backends, + const std::vector& inputShape, + const std::vector& axisShape, + std::vector& outputShape, + std::vector& inputValues, + std::vector& expectedOutputValues, + OutputT axisValue, + tflite::TensorType outputType, + float quantScale = 1.0f, + int quantOffset = 0) +{ + using namespace tflite; + std::vector modelBuffer = CreateArgMinMaxTfLiteModel(argMinMaxOperatorCode, + tensorType, + inputShape, + axisShape, + outputShape, + {axisValue}, + outputType, + quantScale, + quantOffset); + + const Model* tfLiteModel = GetModel(modelBuffer.data()); + CHECK(tfLiteModel != nullptr); + + std::unique_ptr armnnDelegateInterpreter; + CHECK(InterpreterBuilder(tfLiteModel, ::tflite::ops::builtin::BuiltinOpResolver()) + (&armnnDelegateInterpreter) == kTfLiteOk); + CHECK(armnnDelegateInterpreter != nullptr); + CHECK(armnnDelegateInterpreter->AllocateTensors() == kTfLiteOk); + + std::unique_ptr tfLiteInterpreter; + CHECK(InterpreterBuilder(tfLiteModel, ::tflite::ops::builtin::BuiltinOpResolver()) + (&tfLiteInterpreter) == kTfLiteOk); + CHECK(tfLiteInterpreter != nullptr); + CHECK(tfLiteInterpreter->AllocateTensors() == kTfLiteOk); + + // Create the ArmNN Delegate + armnnDelegate::DelegateOptions delegateOptions(backends); + std::unique_ptr + theArmnnDelegate(armnnDelegate::TfLiteArmnnDelegateCreate(delegateOptions), + armnnDelegate::TfLiteArmnnDelegateDelete); + CHECK(theArmnnDelegate != nullptr); + // Modify armnnDelegateInterpreter to use armnnDelegate + CHECK(armnnDelegateInterpreter->ModifyGraphWithDelegate(theArmnnDelegate.get()) == kTfLiteOk); + + // Set input data + armnnDelegate::FillInput(tfLiteInterpreter, 0, inputValues); + armnnDelegate::FillInput(armnnDelegateInterpreter, 0, inputValues); + + // Run EnqueueWorkload + CHECK(tfLiteInterpreter->Invoke() == kTfLiteOk); + CHECK(armnnDelegateInterpreter->Invoke() == kTfLiteOk); + + // Compare output data + auto tfLiteDelegateOutputId = tfLiteInterpreter->outputs()[0]; + auto tfLiteDelageOutputData = tfLiteInterpreter->typed_tensor(tfLiteDelegateOutputId); + auto armnnDelegateOutputId = armnnDelegateInterpreter->outputs()[0]; + auto armnnDelegateOutputData = armnnDelegateInterpreter->typed_tensor(armnnDelegateOutputId); + + for (size_t i = 0; i < expectedOutputValues.size(); i++) + { + CHECK(expectedOutputValues[i] == armnnDelegateOutputData[i]); + CHECK(tfLiteDelageOutputData[i] == expectedOutputValues[i]); + CHECK(tfLiteDelageOutputData[i] == armnnDelegateOutputData[i]); + } +} + +} // anonymous namespace \ No newline at end of file -- cgit v1.2.1