From 6f92c8e9f8bb38dcf5dccf8deeff5112ecd8e37c Mon Sep 17 00:00:00 2001 From: Nikhil Raj Date: Wed, 22 Nov 2023 11:41:15 +0000 Subject: Update Doxygen for 23.11 Signed-off-by: Nikhil Raj Change-Id: I47cd933f5002cb94a73aa97689d7b3d9c93cb849 --- .../classarmnn_1_1_ref_base_workload-members.html | 130 +++++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 23.11/classarmnn_1_1_ref_base_workload-members.html (limited to '23.11/classarmnn_1_1_ref_base_workload-members.html') diff --git a/23.11/classarmnn_1_1_ref_base_workload-members.html b/23.11/classarmnn_1_1_ref_base_workload-members.html new file mode 100644 index 0000000000..9c48c28698 --- /dev/null +++ b/23.11/classarmnn_1_1_ref_base_workload-members.html @@ -0,0 +1,130 @@ + + + + + + + + +Arm NN: Member List + + + + + + + + + + + + + + + + +
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RefBaseWorkload< QueueDescriptor > Member List
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This is the complete list of members for RefBaseWorkload< QueueDescriptor >, including all inherited members.

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BaseWorkload(const QueueDescriptor &descriptor, const WorkloadInfo &info)BaseWorkload< QueueDescriptor >inline
Execute() const =0IWorkloadpure virtual
ExecuteAsync(ExecutionData &executionData) overrideBaseWorkload< QueueDescriptor >inlinevirtual
GetData() constBaseWorkload< QueueDescriptor >inline
GetGuid() const finalBaseWorkload< QueueDescriptor >inlinevirtual
GetMemoryRequirements()IWorkloadinlinevirtual
GetName() const overrideBaseWorkload< QueueDescriptor >inlinevirtual
m_DataBaseWorkload< QueueDescriptor >protected
m_GuidBaseWorkload< QueueDescriptor >protected
m_NameBaseWorkload< QueueDescriptor >protected
PostAllocationConfigure() overrideBaseWorkload< QueueDescriptor >inlinevirtual
RefBaseWorkload(const QueueDescriptor &descriptor, const WorkloadInfo &info)RefBaseWorkload< QueueDescriptor >inline
RegisterDebugCallback(const DebugCallbackFunction &)IWorkloadinlinevirtual
ReplaceInputTensorHandle(ITensorHandle *tensorHandle, unsigned int slot) overrideRefBaseWorkload< QueueDescriptor >inlinevirtual
ReplaceOutputTensorHandle(ITensorHandle *tensorHandle, unsigned int slot) overrideRefBaseWorkload< QueueDescriptor >inlinevirtual
SupportsTensorHandleReplacement() const overrideRefBaseWorkload< QueueDescriptor >inlinevirtual
~IWorkload()IWorkloadinlinevirtual
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