From 6f92c8e9f8bb38dcf5dccf8deeff5112ecd8e37c Mon Sep 17 00:00:00 2001 From: Nikhil Raj Date: Wed, 22 Nov 2023 11:41:15 +0000 Subject: Update Doxygen for 23.11 Signed-off-by: Nikhil Raj Change-Id: I47cd933f5002cb94a73aa97689d7b3d9c93cb849 --- 23.11/_ref_arg_min_max_workload_8cpp_source.html | 199 +++++++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 23.11/_ref_arg_min_max_workload_8cpp_source.html (limited to '23.11/_ref_arg_min_max_workload_8cpp_source.html') diff --git a/23.11/_ref_arg_min_max_workload_8cpp_source.html b/23.11/_ref_arg_min_max_workload_8cpp_source.html new file mode 100644 index 0000000000..0f8bfd217e --- /dev/null +++ b/23.11/_ref_arg_min_max_workload_8cpp_source.html @@ -0,0 +1,199 @@ + + + + + + + + +Arm NN: src/backends/reference/workloads/RefArgMinMaxWorkload.cpp Source File + + + + + + + + + + + + + + + + +
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+  23.11 +
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RefArgMinMaxWorkload.cpp
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+Go to the documentation of this file.
1 //
+
2 // Copyright © 2019-2023 Arm Ltd and Contributors. All rights reserved.
+
3 // SPDX-License-Identifier: MIT
+
4 //
+
5 
+ +
7 
+
8 #include "ArgMinMax.hpp"
+
9 #include "RefWorkloadUtils.hpp"
+
10 #include "Decoders.hpp"
+
11 #include "Encoders.hpp"
+
12 #include "Profiling.hpp"
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13 
+
14 namespace armnn
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15 {
+ +
17  const ArgMinMaxQueueDescriptor& descriptor,
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18  const WorkloadInfo& info)
+ +
20 
+
21 
+ +
23 {
+ +
25 }
+
26 
+ +
28 {
+
29  WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
+
30  Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
+
31 }
+
32 
+
33 void RefArgMinMaxWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
+
34 {
+
35  ARMNN_SCOPED_PROFILING_EVENT_REF_NAME_GUID("RefArgMinMaxWorkload_Execute");
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36 
+
37  const TensorInfo &inputTensorInfo = GetTensorInfo(inputs[0]);
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38 
+
39  std::unique_ptr<Decoder<float>> decoderPtr = MakeDecoder<float>(inputTensorInfo, inputs[0]->Map());
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40  Decoder<float> &decoder = *decoderPtr;
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41 
+
42  const TensorInfo &outputTensorInfo = GetTensorInfo(outputs[0]);
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43 
+
44  if (outputTensorInfo.GetDataType() == armnn::DataType::Signed32) {
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45  int32_t *output = GetOutputTensorData<int32_t>(outputs[0]);
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46  ArgMinMax(decoder, output, inputTensorInfo, outputTensorInfo, m_Data.m_Parameters.m_Function,
+ +
48  } else {
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49  int64_t *output = GetOutputTensorData<int64_t>(outputs[0]);
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50  ArgMinMax(decoder, output, inputTensorInfo, outputTensorInfo, m_Data.m_Parameters.m_Function,
+ +
52  }
+
53 }
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54 
+
55 } //namespace armnn
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+
+
void ExecuteAsync(ExecutionData &executionData) override
+ + + + +
ArgMinMaxFunction m_Function
Specify if the function is to find Min or Max.
Definition: Descriptors.hpp:81
+
#define ARMNN_SCOPED_PROFILING_EVENT_REF_NAME_GUID(label)
Creates a profiling event that uses GetGuid() and GetName() from the calling class.
+
RefArgMinMaxWorkload(const ArgMinMaxQueueDescriptor &descriptor, const WorkloadInfo &info)
+ +
void ArgMinMax(Decoder< float > &in, OUT *out, const TensorInfo &inputTensorInfo, const TensorInfo &outputTensorInfo, ArgMinMaxFunction function, int axis)
Definition: ArgMinMax.cpp:17
+
Contains information about TensorInfos of a layer.
+
const TensorInfo & GetTensorInfo(const ITensorHandle *tensorHandle)
float32 helpers
+ + + +
DataType GetDataType() const
Definition: Tensor.hpp:198
+
std::vector< ITensorHandle * > m_Outputs
+ + + + + + + +
Copyright (c) 2021 ARM Limited and Contributors.
+
int m_Axis
Axis to reduce across the input tensor.
Definition: Descriptors.hpp:83
+ + + + + +
std::vector< ITensorHandle * > m_Inputs
+ + + + + -- cgit v1.2.1