From 6f92c8e9f8bb38dcf5dccf8deeff5112ecd8e37c Mon Sep 17 00:00:00 2001 From: Nikhil Raj Date: Wed, 22 Nov 2023 11:41:15 +0000 Subject: Update Doxygen for 23.11 Signed-off-by: Nikhil Raj Change-Id: I47cd933f5002cb94a73aa97689d7b3d9c93cb849 --- ...ectional_sequence_lstm_float_workload_8cpp.html | 143 +++++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 23.11/_cl_unidirectional_sequence_lstm_float_workload_8cpp.html (limited to '23.11/_cl_unidirectional_sequence_lstm_float_workload_8cpp.html') diff --git a/23.11/_cl_unidirectional_sequence_lstm_float_workload_8cpp.html b/23.11/_cl_unidirectional_sequence_lstm_float_workload_8cpp.html new file mode 100644 index 0000000000..5e7230cf22 --- /dev/null +++ b/23.11/_cl_unidirectional_sequence_lstm_float_workload_8cpp.html @@ -0,0 +1,143 @@ + + + + + + + + +Arm NN: src/backends/cl/workloads/ClUnidirectionalSequenceLstmFloatWorkload.cpp File Reference + + + + + + + + + + + + + + + + +
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ClUnidirectionalSequenceLstmFloatWorkload.cpp File Reference
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+Include dependency graph for ClUnidirectionalSequenceLstmFloatWorkload.cpp:
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Go to the source code of this file.

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 armnn
 Copyright (c) 2021 ARM Limited and Contributors.
 
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+Functions

arm_compute::Status ClUnidirectionalSequenceLstmFloatWorkloadValidate (const TensorInfo &input, const TensorInfo &outputStateIn, const TensorInfo &cellStateIn, const TensorInfo &outputStateOut, const TensorInfo &cellStateOut, const TensorInfo &output, const UnidirectionalSequenceLstmDescriptor &descriptor, const LstmInputParamsInfo &paramsInfo)
 
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