From 6f92c8e9f8bb38dcf5dccf8deeff5112ecd8e37c Mon Sep 17 00:00:00 2001 From: Nikhil Raj Date: Wed, 22 Nov 2023 11:41:15 +0000 Subject: Update Doxygen for 23.11 Signed-off-by: Nikhil Raj Change-Id: I47cd933f5002cb94a73aa97689d7b3d9c93cb849 --- 23.11/_cl_logical_not_workload_8cpp_source.html | 192 ++++++++++++++++++++++++ 1 file changed, 192 insertions(+) create mode 100644 23.11/_cl_logical_not_workload_8cpp_source.html (limited to '23.11/_cl_logical_not_workload_8cpp_source.html') diff --git a/23.11/_cl_logical_not_workload_8cpp_source.html b/23.11/_cl_logical_not_workload_8cpp_source.html new file mode 100644 index 0000000000..231e1357ed --- /dev/null +++ b/23.11/_cl_logical_not_workload_8cpp_source.html @@ -0,0 +1,192 @@ + + + + + + + + +Arm NN: src/backends/cl/workloads/ClLogicalNotWorkload.cpp Source File + + + + + + + + + + + + + + + + +
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+  23.11 +
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ClLogicalNotWorkload.cpp
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+Go to the documentation of this file.
1 //
+
2 // Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved.
+
3 // SPDX-License-Identifier: MIT
+
4 //
+
5 
+
6 #include "ClLogicalNotWorkload.hpp"
+
7 
+
8 #include "ClWorkloadUtils.hpp"
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9 
+
10 #include <armnn/utility/PolymorphicDowncast.hpp>
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11 
+
12 #include <aclCommon/ArmComputeTensorUtils.hpp>
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13 
+
14 #include <cl/ClTensorHandle.hpp>
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15 
+
16 namespace armnn
+
17 {
+
18 using namespace armcomputetensorutils;
+
19 
+
20 arm_compute::Status ClLogicalNotWorkloadValidate(const TensorInfo& input,
+
21  const TensorInfo& output)
+
22 {
+
23  const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input);
+
24  const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output);
+
25 
+
26  const arm_compute::Status aclStatus = arm_compute::CLLogicalNot::validate(&aclInputInfo,
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27  &aclOutputInfo);
+
28  return aclStatus;
+
29 }
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30 
+
31 ClLogicalNotWorkload::ClLogicalNotWorkload(const ElementwiseUnaryQueueDescriptor& descriptor,
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32  const WorkloadInfo& info,
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33  const arm_compute::CLCompileContext& clCompileContext)
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34  : ClBaseWorkload<ElementwiseUnaryQueueDescriptor>(descriptor, info)
+
35 {
+
36  // Report Profiling Details
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37  ARMNN_REPORT_PROFILING_WORKLOAD_DESC("ClLogicalNotWorkload_Construct",
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38  descriptor.m_Parameters,
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39  info,
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40  this->GetGuid());
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41 
+
42  m_Data.ValidateInputsOutputs("ClLogicalNotWorkload", 1, 1);
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43 
+
44  arm_compute::ICLTensor& input = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
+
45  arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
+
46 
+
47  {
+
48  ARMNN_SCOPED_PROFILING_EVENT_CL_NAME_GUID("ClLogicalNotWorkload_configure");
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49  m_LogicalNotLayer.configure(clCompileContext, &input, &output);
+
50  }
+
51 }
+
52 
+
53 void ClLogicalNotWorkload::Execute() const
+
54 {
+
55  ARMNN_SCOPED_PROFILING_EVENT_CL_NAME_GUID("ClLogicalNotWorkload_Execute");
+
56  m_LogicalNotLayer.run();
+
57 }
+
58 
+
59 } // namespace armnn
+
+
+
armnn::QueueDescriptor::ValidateInputsOutputs
void ValidateInputsOutputs(const std::string &descName, unsigned int numExpectedIn, unsigned int numExpectedOut) const
Definition: WorkloadData.cpp:446
+ + +
armnn::ClLogicalNotWorkload::Execute
virtual void Execute() const override
Definition: ClLogicalNotWorkload.cpp:53
+ +
ARMNN_SCOPED_PROFILING_EVENT_CL_NAME_GUID
#define ARMNN_SCOPED_PROFILING_EVENT_CL_NAME_GUID(label)
Creates a profiling event that uses GetGuid() and GetName() from the calling class.
Definition: ClWorkloadUtils.hpp:36
+ +
armnn::WorkloadInfo
Contains information about TensorInfos of a layer.
Definition: WorkloadInfo.hpp:16
+ + + + +
armnn::QueueDescriptor::m_Outputs
std::vector< ITensorHandle * > m_Outputs
Definition: WorkloadData.hpp:27
+
ARMNN_REPORT_PROFILING_WORKLOAD_DESC
#define ARMNN_REPORT_PROFILING_WORKLOAD_DESC(name, desc, infos, guid)
Definition: Profiling.hpp:227
+
armnn::Status
Status
Definition: Types.hpp:42
+ + +
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_quick_start.dox:6
+ +
armnn::ClLogicalNotWorkload::ClLogicalNotWorkload
ClLogicalNotWorkload(const ElementwiseUnaryQueueDescriptor &descriptor, const WorkloadInfo &info, const arm_compute::CLCompileContext &clCompileContext)
Definition: ClLogicalNotWorkload.cpp:31
+
armnn::ClLogicalNotWorkloadValidate
arm_compute::Status ClLogicalNotWorkloadValidate(const TensorInfo &input, const TensorInfo &output)
Definition: ClLogicalNotWorkload.cpp:20
+
armnn::QueueDescriptor::m_Inputs
std::vector< ITensorHandle * > m_Inputs
Definition: WorkloadData.hpp:26
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